Current Type D Class Research And Design Rf Power Amplifier And Digital Transmitter

High efficiency CMOS Radio Frequency (RF) switching mode power amplifier (PA) and all digital transmitters are studied in this thesis.The research of CMOS RF PA was mainly focused on the linear amplifiers in the past decades. Recently, communication technology has been widely used in portable devices. The power efficiency of RF transmitter is becoming more and more important. The traditional linear PA cannot overcome the drawback of low efficiency, while switch PA’s advantage of high efficiency is drawing researchers’attentions. Under this background, this thesis has designed a high efficiency current mode Class-D (CMCD) RF PA. Traditional CMCD PA uses an inductor as a core of its resonate circuits, but it also needs output matching circuits and Balun to achieve impedance matching and differential to single ended conversion. To improve the integrity of the PA, an on-chip transformer is designed and integrated in the CMCD circuits. The transformer accompanied with two capacitors achieve impedance transformation, resonate circuits and single ended output. After analyzing several key mechanisms of power losses in CMCD, a method towards efficiency-optimized design is proposed, as well as the design methodology to improve efficiency of the on-chip transformer. The transformer’s equivalent lumped circuit is built and its parameters extraction from electro-magnetic simulation is introduced.It has been a trend to replace analog/RF circuits with digital circuits as much as possible, which can take the advantage of high speed and low power in today’s advanced CMOS technology. This thesis focuses on the digitalized RF transmitter. It utilizes a1-bit digital SA modulator to drive a switch PA. This architecture is called Class-S and is a kind of high efficiency solution for transmitting RF. The design of interpolator, digital mixer, band-pass∑△modulator and a whole system model are included in this thesis.The designed CMCD PA has been fabricated and verified with TSMC65nm CMOS process. The chip takes an area of0.6×1.3mm2. With1.5V supply, the measured output power is24.7dBm at2GHz frequency, and its peak PAE is46.6%. The results are close to the expected value.