Fundamental performance limits and scaling of a CMOS passive double-balanced (FET-Quad) mixer

In this thesis, fundamental performance limits and scaling of a passive double-balanced mixer are examined. Analysis of the passive double-balanced mixer will show how its performance metrics are directly affected by the down-scaling of the transistor gate length, Lg. We analyze the performance in terms of conversion gain (GC), 1-dB compression point, and Noise Figure (NF). We will show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance. This is verified through simulation and model results for mixers designed in CMOS 350nm to 32nm technology. We measure and present the results of a 0.13um passive double-balanced mixer which is used to verify our model and simulations. We introduce two new mixer figures-of-merit (FOMMIXER ) to compare performance with technology scaling. Circuit designers and System architects can use this thesis to find a suitable process technology that will meet their specifications when designing a FET-Quad mixer.