Hardening Design Of Single Event Upset In DRAM

Once high-energy particles pass through semiconductor, a lot of free charges will be generated along the track. These charges can be collected by sensitive nodes and stored data will be upset. Dynamic random access memories(DRAM) are widely used with the advantages of low cost and high integration density. The probability of single event upset(SEU) in DRAM is gradually increasing with the growing density. Different methods must be adopted to improve reliability. The radiation-hardening methods are studied from two aspects of memory cell and error correction code in this thesis.The mechanism of SEU in DRAM is introduced according to the principle of DRAM.Moreover, the verification of the funnel model and simulation of SEU are completed based on the circuit model and device model of the memory cell. The upset LET threshold value is 0.06 p C/?m. Then the two known hardening designs named storage-node-boosted(SNB)and cell-plate line connecting complementary bit-line(C3) are discussed. A new hardening design named boosted C3 is proposed based on the advantages of SNB and C3. The stored charge is increased by controlling the voltage of cell-plate line. Meanwhile, a transistor is added to connect the complementary bit-line with the cell-plate line. The charge redistribution between bit-line, complementary bit-line and storage capacitor results in an enhanced readout signal. The critical charge is increased and the upset LET value is up to0.55 p C/?m which reduces the probability of SEU.The hardening design of DRAM memory cell can enhance the resistance to the SEU directly, but the stored data will be wrong when the radiation dose exceeds the upset LET.So, error correction codes can be used to recover the data. The principle of one bit error correction, double error detection, double adjacent error correction(SEC-DED-DAEC)code is analyzed based on the theory of line block code. By adding the vectors with the hamming weight of 5, the miscorrection probability of non-adjacent double errors is reduced. The check matrixes of(22,16),(39,32),(72,64) are obtained by combining Greedy algorithm and Backtracking algorithm.With adding one additional check bit to increase the types of syndromes, the check matrixes of(23,16),(40,32),(73,64) are obtained and the miscorrection probability is reduced by 7%. Then the mean time to failure(MTTF) of unprotected memory and memory with single error correction, double error detection(SEC-DED) code and memory with SEC-DED-DAEC code are compared with each other. The result shows that the MTTF of memory with SEC-DED-DAEC code is20% longer than that of the memory with SEC-DED code and 200% larger than that of the unprotected memory on average.The error detection and correction circuit of(23,16) code is designed in verilog and synthesized in the SMIC 0.13?m process conditions. The overhead of the code proposed is reduced by 6.2% compared with that of other similar codes.