Design And Implementation Of A Congestion-controlled Network On Chip

Digitalization puts forward higher requirements on the performance of integrated circuits. Moore's law has steadily increased on-chip transistor densities and enabled the integration of many components on a single die. With the integration of multiple functions, IPs(Intellectual Property) designed by different companies are used in a design to develop So Cs(System-on-Chip). In a digital system, IPs communicate with each other and process the exchanged data seperately. Shared buses and other forms of interconnect featuring long global wires are unable to keep up with the increasing communication performance requirements. Derived from the Internet's distributed routing mechanism, a new communication structure, i.e. No C(Network-on-chip), becomes more attractive and pervasive in So C designs. No C provides high bandwidth, low latency, low cost and is easily scalable.This thesis made research in network congestion problem of 2D Mesh No C. Several improvements were made on 3 aspects to mitigate network congestion, aiming at a better communication performance. First, a new topology was put forward. It connected the unused I/Os of fringe routers to get more datapaths for traffic diversion and then reduced congestion. Redirection strategy was devised to achieve traffic diversion. Second, a new adaptive routing algorithm was designed based upon turn model and local congestion information. Third, an injection-control module was introduced on Local input port to adjust the injection rate of data and then the network congestion was relieved.The design was realized at RTL level using Verilog HDL and simulated in Modelsim to verify the expected function. Then the design was tested under a standard testing platform. Compared with No C using DOR algorithm and basic Mesh topoloty, this design have achieved throughput increases by 6.6%, 25.6%, 29.8%, 14.8%, 32.5%, 23.5% respectively at traffic patterns—Random, Transpose1, Transpose2, Shuffle, Butterfly, Bit_reversal, and then smaller average latency. In the end, the design was synthesized in Design Compiler with SMIC 65 nm library at 300 MHz. It could satisfy the timing requirements at this clock frequency and its netlist area was 991K? m2 with an overhead of 4.5% compared to the basic No C mentioned above. The results show that this design has improvements in performance with an acceptable area overhead and that the network congestion is relieveddue to the changes we've made.