Hardware Platform Design And Implementation On RF Front End Of Receiver In L-band

As one of the core components on communications equipment, L-band receiver has an extremely important value in military and civilian applications. With the rapid development of wireless communication technology and increasing spectrum utilization, the performance indicators what receiver design should achieve are getting more and more harsh. The RF front end of receiver is rather important throughout the design process, its performance will affect baseband directly and the overall receiver system indirectly. Thus we should in-depth study on the design of RF front end. Especially in complex electromagnetic interference environment, it is a relatively big challenge.In this paper, the L-band receiver RF front-end hardware platform is designed and implemented. Combing the NF(<5dB),the wideband(1150MHz-1550MHz), the stray(<-55dBC), the maximum conversion gain(80dB) and IF output(70MHz±11MHz) in the indicators, we select the two downconverted IF formula by comparing the current common receiver architecture.By using Genesys and ADS simulation software to select frequency plan, we analyze the distribution of stray in the band and determine IF to be 440MHz.Meanwhile we budget LNA gain 15dB, the gain of first and second stage amplifier circuit each 40dB.At last we demonstrate the feasibility of overall system design by entering a different intensity 1350MHz tone signal on the overall spurious analysis.We research and simulate the key technologies of the RF front-end, including the matching, bias circuit design and stability analysis in LNA, combining high frequency resolution (1MHz), very short switching times (20us) requirements in the indicators, choose a dual PLL ping-pong mode as the local oscillator 1 design, PLL with VCO as the local oscillator 2 design. On the AGC design,we use the program that insert a PIN diode attenuator to control the overall gainadopting at L-port input channels, IF 1 and IF 2. Only in this way,we can ensure 70MHz IF output port's power is OdBm, by using detection to start controlling three attenuators' activity and reach a high dynamic gain (80dB).By using the simulation results, we design the filter, low noise amplifier, a mixer, a frequency synthesizer system, AGC circuit, FPGA and peripheral circuits schematics. Since the frequency synthesis system is particularly important on the whole design, we detailedly demonstrate the selection of the main device, simulate and analyse the phase noise by ADIsimPLL and Hittite PLL Design Simulation Tool for clock divider and PLL, finally selecte a practical program as the system frequency source.Finally, we use the Cadence Allegro to design the eight-story mixed-signal design hardware platform, taking into account the electromagnetic compatibility, crosstalk, reflections and other factors, the borad is splited by the RF circuits, digital circuits and power modules. After welding commissioning, we test the 70MHz ± 11 MHz output signal power, spectral purity, the indicators frequency synthesizer output frequency, phase noise and AGC, find that the platform basically meet the requirements.