64-bit Mips-based Embedded System Dynamic Simulation Technology Research

An instruction-set simulator is a tool that runs on a host machine to mimic the behavior of running an application program on a target machine. It is an important tool for computer architecture research and software and hardware co-design. In the past few years, instruction set simulators are indispensable part in process of design of embedded processors.With the processor hardware innovation and improvement, the existing instruction set simulator has been unable to adapt to the current hardware requirements. Over the past decades, most of the simulator researches are based on 32-bit processors. Simulator researches based on 64-bit processors are very little. An example is that most of the exiting simulators are 32-bit simulators; its performance and flexibility to meet the current hardware demands are not good. Therefore, the introduction of new technology to develop a new kind of simulator has an important significance. With the increasing application of 64-bit processors, the processor simulation field must face a new challenge. For example, what kind of hardware description language should be adapted and how to realize parallel process, etc. are all exiting difficulties at present. And that the MIPS64 ISS based on the 64-bit dynamic translation technology not only meet the needs of the MIPS64 embedded simulator, but also it should be fully compatible with 32-bit MIPS embedded simulator. So the dynamic simulation and research base on 64-bit MIPS embedded system is of great significance to develop MIPS embedded system and improves system performance.The main works of this paper are: Firstly, Create Cross Compiler based on the newlib. To make the Cross Compiler'transplantation more convenient, speed up the compile procedure and support MIPS64 instruction set.In this paper, we realized MIPS-elf-* style Cross Compiler which based on the newlib. Secondly, realise a MIPS32 and MIPS64 compatible ISS. It simulates all the MIPS processor instructions except float instructions. The main instructions include arithmatic instructions, load and store instructions, branch and coprocessor instructions. To improve decoding speed, a multi-level index decoding technology is used during the decoding process instead of using the traditional code generator. Additional, because the MIPS32 instruction set is a subset of MIPS64 instruction set, we use C++ template to realise the compatibility of MIPS32 and MIPS64 ISS, Thus it greatly improves the reusability of the code. Thirdly, in order to compare the performance of different instruction set simulation techniques, this paper implements interpretive simulation mode, unspecific dynamic compiled simulation mode. We use Cache to save the instructions in the unspecific dynamic compiled simulator. At last, we use asm lanuage write a lot of test program to make sure the simulated instruction sets can work correctly. This technique independent of the host machines (both machine architecture and operating system), as long as the host platforms support C++ language. Experimental results show that the instruction set simulation technique which used in this paper can simulate the instruction sets of MIPS processor correctly; this technique has a high simulation speed.