Design And Implementation Of Multi-target Instruction Set Simulator

Instruction Set Simulator (ISS) is widely used in code analysis and execution simulation, but most of traditional instruction set simulators are designed for particular processor architecture. This thesis makes research on the instruction set simulation technique that supports a wide range of processor architectures; design a simulation environment for different kinds of processors, as is designed for the program simulation and instruction flow analysis.This thesis research the related technique of instruction set simulation, including the classification of simulators, simulation driven approach and simulation strategy. Combined with the typical examples of Micro Processor Unit(MPU), Micro Controller Unit(MCU) and Digital Signal Processor(DSP), the typical structural features of embedded processors are summarized. Using the hierarchical design technology and plug-in technology, a multi-target instruction simulator that supports multi-processor architecture is designed, which divides the simulator into three layers including user interface, communication interface and the functional simulation layer, and design the relationship and interfaces between them. Also, expound the details of design and implementation of the functional simulation from the hardware resources simulation, instruction execution, interruption mechanism, and so on.At last, thesis takes 8051 and ARM7 processor plug-in as examples to takes functional and performance testing. Testing result shows that the multi-target instruction set simulator achieves the request of design, as well as stable performance, and the framework of multi-target simulator can adapt to different processor architectures.