High-speed Dual-field Elliptic Curve Digital Signature Hardware-accelerated Research And Implementation

In today's electronic information age, information security issues are also increasingly prominent with the rapid development of technology, how to ensure security in an insecure network communication becomes an issue of growing concern. Digital signature technology is a new application for the matter of information security derived by cryptography. It can provide message authenticity, integrity, and non-repudiation during transmission over any insecure network. ECDSA,the signature algorithm based on the elliptic curve, is widely used and developed for the advantages of high safety, short key and fast speed.For the requirement of real-time response, the elliptic curve signature algorithm implemented in software can not meet the demand, and could easily be attacked. At present, there are several researches about hardware implementation of the elliptic curve digital signature algorithm. But the researches are mainly for single finite field, GF(p)field or GF(2m) field, and can only support specific length of operand. So its application is limited, and can not be configured with the security needs of different application environments.Based on the system security considerations, this article firstly studied and proposed improvement measures for the elliptic curve digital signature algorithm security; then it proposed the use of the software and hardware co-design means to implement the ECDSA algorithm in order to improve processing speed, the hardware is used for acceleration, and the software use the underlying hardware to control the flow of the protocol, and the architecture use the pipeline and parallel operation units. The designed hardware architecture has good scalability and flexibility, it can support dual finite field operations of GF(p) and GF(2m), and can also support operands of different bit width less than 768 bits.After completing the hardware design, the article tested the function of all hardwaremodules based Modelsim, and used the Xilinx KC705 FPGA for the circuit implementation. Then it discussed the impact of different design parameters on circuit performance. This article also completed circuit ASIC implementation based on SMIC0.13?m CMOS technology and finally successfully taped. The test results show that the highest work frequency of the design is 109 MHz, the area of the circuit is894923.734?m2, that is 221 k equivalent logic gates. For the calculation of 192 bit operand, in GF(p) field the time of the signature is 562?s; in GF(2m) field, the time of the signature is 515?s. Compared with the relevant literature, the speed of this article is faster,and it can support dual finite field arithmetic and operands of different bit width, the architecture has good scalability and flexibility.