Design Of Hardware Implementation Of ECDSA Signature Algorithm And Its FPGA Simulation

With the rapid development of mobile Internet and information technology,the issue of how to ensure the secure transmission of information in wireless networks is getting more and more attention.The public key cryptosystem is one of the important technology for im-plementing the secure transmission of information.,especially,the elliptic curve public-key cryptosystem(ECC).it has the advantages of high security,short key length,fast calculation speed,saving communication bandwidth and saving storage space.The security of 160-bit ECC is equivalent to that of 1024-bit RSA.Digital signature technology is an important se-curity technology that simulates the traditional signature method to ensure the secure trans-mission of information.The ECDSA signature algorithm based on the ELGamal system has the advantages of the elliptic curve cryptosystem.ECDSA signature algorithm has been widely used in various fields and has been designated as an international standard by many international standards organizations.It is especially suitable for some application areas with limited computing capacity and limited storage space,such as wineless network envi-ronment.Considering the performance requirements of wireless devices in terms of resource occupation,computing power,and system security,the optimization and design implemen-tation of ECDSA signature algorithms has always been an important research field.In this thesis the hardware architecture and environmentits components of the ECDSA sig-nature algorithm is designed and implemented based on the verilog hardware description language,and a functional simulation verification is performed based on the FPGA develop-ment board.The hardware system architecture of the ECDSA signature algorithm mainly includes a core computing module and a signature module.The core computing module mainly performs algorithm optimization and design implementation of scalar multiplication operations.In this thesis,the 3bit combined scalar multiplication operation is optimized.A 3bit combined scalar multiplication arithmetic module based on the zero-run distribution is designed and implemented,Which improves the efficiency by 45%.The signature module includes a binary domain operation module and a prime domain operation module.The bi-nary domain arithmetic module uses a Gaussian normal basis,mainly including multiplica-tion operations,inverse operations,addition operations,and square operations.At the same time,the multiplication operation is designed by using the Montgomery algorithm on the prime domain operation module,and the inverse operation is designed and implemented by using the improved stein algorithm.To avoid inverse calculations occupying too much sys-tem resources and affecting performance,an elliptic curve group operation is implemented based on LD projection coordinates.Finally,the core modules of the ECDSA algorithm sys-tem architecture are simulated and verified on the FPGA development board using Vivado and Modelsim.In addition,the characteristics of the FourQ curve and the scalar multiplica-tion of the FourQ curve are studied,and its hardware architecture of the scalar multiplication operation is completed.In this thesis,in order to analyze the resoure comsumption and systme performance,the sys-tem architecture of ECDSA algorithm and its signature module and core computing module is simulated and tested using the latest development kit of KINTEX7 from Xilinx.The test results show that our design achieved a good computing performance.