An Optimized Design Of Low Phase-noise Synthesizer Based On DDS And PLL

With the development of computer technology in modern society, the workload of network communication is increasing day by day, which is a huge challenge in terms of modern communication systems, especially for frequency stability and accuracy of communications equipment. Development of IoT, radar, test equipment and other aspects will need a high performance frequency synthesizer to provide the signal source, which proposed higher requirements for frequency range, phase noise and spurious performance, frequency stability and time hopping of the frequency synthesizers. Based on the development of information and communication industry, the frequency synthesizers, as a key module of the electronic communication system, has a huge market demand and broad development prospects, which makes engineers to carry out constantly upgrade and improve its performance.Firstly, this article introduces the relevant concept and implementation of frequency synthesis techniques, and then describes the domestic and international developments and research background of PLL frequency synthesizer technology. Next, we introduce the basic theoretical of the phase-locked loop and analysis of its phase noise and spurious performance. Then, in order to optimize the DDS module, we study and discuss a variety of DDS + PLL systems, then design a pre-locking structure to assist locking to make easy to filter. On the basis of both the cost and the complexity of the system, we design a structure of DDS inserted PLL with dual-PLLs.Based on the final design, we do some work of device selection, circuit simulation and PCB design, complicate the fabrication of the frequency synthesizer. Test result shows that the phase noise is better than-115dBc/Hz@10kHz and spurious suppression is better than-67 dBc. Then we make suggestions for improvement at last.