Research And Design Of On-chip LDO With High Stability And Fast Load Transient Response

LDO with its low cost,low noise and fast transient response is widely used in electronic equipment as an important member of the power management IC.LDO can be divided into two kinds:with external capacitance and without external capacitance(on-chip LDO).With the development of SOC technology,various functions are integrated on a chip.LDO integrated on the chip can promote the power supply performance of the chip and save production cost.So the on-chip LDO is the present research hotspot.The design difficulty of LDO without external capacitance lies in load stability and transient response performance within the range of all load conditions.This paper focuses on the high stability and fast transient response characteristics of LDO.And then,the frequency characteristic of tertiary structure LDO and nested miller compensation(NMC)principle as well as its stability condition are analyzed by formula derivation.A LDO based on improved enhanced AB follower is designed.It changes AB follower to dynamic bias current circuit to accelerate the transient response and uses NMC to maintain more than 60 degrees phase margin when the load current is more than 100μA.The LDO based on push-pull circuit which has positive gain and low output resistance is designed.Based on NMC,the second and the third pole are designed as the conjugate complex poles which can be located beyond the unit gain bandwidth by carefully designing the gain and output resistance buffer level.Thus,the loop has enough phase margin.By analyzing the principle of transient response enhancement technology in on-chip LDO,it can be concluded that the adjusting speed of gate voltage of PMOS adjusting transistor is the important factor that affect the transient performance of LDO.A transient enhancement circuit is proposed in this paper.It can test the overshoot or undershoot of output voltage during load jump through RC circuit.The overshoot or undershoot voltage is amplified and converted into pulse current which is used to charge or discharge the gate capacitance of adjusting transistor to shorten the adjustment process and decrease the change of output voltage.The LDO circuit based on the enhanced AB buffer is verified by HSPICE simulation.Simulation result shows that the phase margin is greater than 60° over the range of load capacitance from OpF to 10OpF and load current from 100μA to 100mA.When load current jumps at the speed of 99mA/μs,the maximum undershoot of output voltage is 70mV and the maximum overshoot is 103 mV.The average recovery time is 1.37μs and the static current is only 15μA.The Simulation result of LDO based on push-pull circuit shows that the phase margin is greater than 60° over the range of load capacitance from 0pF to 100pF under any load conditions.When load current jumps at the speed of 99mA/us,the maximum undershoot of output voltage is 51 mV and the maximum overshoot is 43 mV,average recovery time is 1.28μs.The static current is 30μA.The theoretical derivation and simulation results prove that the proposed LDO circuit based on the NMC technology has a certain advantage on the stability and transient response performance.