Design And Implementation Of High Performance LDO IP

For RF ICs and System on Chip（So C）,the fast transient response Capless Low Dropout Regulator（CL-LDO）is integrated as IP（Intellectual Property）.The CL-LDO is an IP（Intellectual Property）integrated within the chip to regulate the voltage of the on-chip system and to reduce the impact of parasitic lines between pads on the system.Therefore,this paper designs and implements the transistor-level topology of the LDO based on the TSMC 0.18μm CMOS process to enable its on-chip integration as IP,with the main focus on optimising its transient response,stability,accuracy and power consumption.A fast transient response capacitorless LDO circuit IP with high current drive capability that can be integrated into So C systems or RF ICs to provide 1.8 V for digital and analogue circuits is designed.the main tasks are as follows:（1）The utilization of the high quiescent current of the class AB error amplifier com-posed of the Flipped Voltage Follower（FVF）is used to improve the swing rate of the error amplifier,and at the same time,when the load current jumps from light load to heavy load,the dynamic biasing of the error amplifier extends the gain bandwidth product of the LDO and realizes the high transient response of the capacitorless LDO.In the case of a jump from heavy load to light load,although the Class AB error amplifier has a good swing rate,it is not possible to discharge the LDO output due to the absence of a large off-chip capac-itor at the LDO output.The simulation results show that,with the assistance of the transi-ent enhancement circuit,when the load current ILOAD changes suddenly between 0 and300m A in 1μs time,the output voltage has a maximum overshoot of 103m V with a recov-ery time of 1.15μs and a maximum downshoot of 143 m V with a recovery time of 0.5μs;it has a good transient recovery capability.（2）LDO at a minimum input voltage of 2.0V,as the load current increases,the power tube enters the linear region,resulting in a decrease in LDO loop gain,a lower linear ad-justment rate LNR and load adjustment rate LDR require an LDO with higher loop gain,so this paper provides CL-LDO loop gain by switching the CL-LDO from a two-stage to a three-stage operating state during heavy load Therefore,this paper provides the loop gain of the CL-LDO by switching the CL-LDO from two-stage to three-stage operation during heavy load,and ensures the stability of the LDO at no load through Cascode Miller com-pensation.Simulation results show that the CL-LDO has the worst stability in the no-load state,with a minimum phase margin of 58°,a low frequency loop gain of 87d B and a bandwidth of 870k Hz;as the load current increases,the phase margin of the CL-LDO in-creases,switching to a three-stage negative feedback system,the loop gain increases to108d B and the bandwidth expands to 1.86MHz;the load current increases and continues to increase,the As the power tube increases decreases,resulting in the loop gain decreasing to80d B,the bandwidth remains at 1.83MHz,the phase margin is 68°,and the CL-LDO is able to remain stable over the full load current range;the LDR is 0.00581m V/m A and the LNR is 0.7375m V/V.（3）A high PSRR,low temperature drift,high precision bandgap reference circuit was designed to improve the output voltage accuracy of the LDO.With matching resistors,a folded Cascode high gain op-amp and low-pass filtering,the designed reference voltage at2.0V supply voltage and TT process angle has a stable output of 1.2500515V within-50°C to 125°C,a temperature coefficient of 5.83PPM/°C,a voltage accuracy of±0.36%,a min-imum PSRR of-37.7d B and a maximum quiescent current of 16.17μA in the frequency range of 1Hz-10GHz,with a good supply voltage rejection ratio and temperature coeffi-cient,and at the same time,low circuit power consumption.The output voltage of the two-stage op-amp operating in closed-loop negative feedback converts the reference volt-age V_BG into a pre-stabilised value V_REF of 1.8V,which varies by 1.895779m V over the full temperature range to achieve a good voltage regulation effect.The output voltage varies by2.080815m V over the full temperature range,and the maximum output noise is131n V （Hz）^1/2 at 1k Hz,which filters out the noise generated by the pre-stage circuit.