Research And Design On Low-dropout Regulator With Ultra Low Power Consumption

Low-dropout regulator(LDO)has the advantages of simple structure,low noise,low power consumption and small package size advantages and is widely used in portable electronic products as a power conversion circuit.No off-chip capacitor LDO does not need to be connected to a specific capacitance,and does not need to increase additional pins,so it could reduce the chip and PCB area,and is becoming a hot spot of present research.This paper focuses on the research and design of ultra low power LDO with no off-chip capacitor.Firstly,several key problems of ultra low power LDO with no off-chip are discussed.To ultra low power LDO,it is mainly focus on how to distribute quiescent current;how to enhance slew rate.To LDO with no off-chip capacitor,it is mainly about how to compensate frequency and how to improve transient characteristics.Besides,the design of the low voltage bandgap reference,the design of high slew rate buffer,the analysis of the frequency compensation and the improvement of the load regulation are also discussed.Finally,an ultra low power LDO with no off-chip capacitor is design based on the previous theoretical study.The 1.5-V 1.5-mA low-dropout regulator(LDO)with no off-chip capacitor and 881 nA quiescent current is designed and implemented by using GSMC 130 nm CMOS process.The LDO main loop adopts three-stage amplifier structure,with dynamically-biased shut feedback structure as an intermediate buffer for driving the pass device.By using nested Miller compensation(NMC),it puts the dominant pole on the output of the first-stage and the non-dominant poles on the output of the buffer and the output of the pass device.Thus,the non-dominant poles realize pole-pole tracking frequency compensation.Measured results shown that the output voltage was stable at 1.5V when its supply was set to be from 1.6 V to 4 V.The quiescent current was less than 881 nA at 1.5 mA output current.As the load current decreased from 1.5 mA to 0 within 100 ns,the ripple of output voltage was less than 95 mV;and when the supply changed within 0.5 V,the ripple of output voltage was less than 36 mV.The designed circuit was validated by the results of the chip test.