The Design Of CMOS Low-dropout Regulator With Fast Load Transient Response

With the rapid development of electronics such as cell phones and computers,which make a higher request to the power management. Linear voltage regulator as animportant type of circuit in power management, it owns many advantages, which hasbeen widely used in various types of electronic equipment. Sort it out according topresence of large external capacitance, there are two types. Transient response andloop stability have always been a top priority of the design performance indexes; Asfor LDO with large output capacitor, the design difficulty lies in how to achieve bothfast loop response while keeping a low quiescent current, and also taking into accountthe problem of loop stability when overloaded. However, the design challenge of thecap-less LDO is that there is no any large capacitor at the output node, which willinevitably lead to a very high peak of the output voltage. Therefore, the loopbandwidth must be large enough to quickly suppress the output peak, while the highbandwidth of the loop may cause the circuit does not work properly at light loads.The main content of the thesis is based on the power supply module in a projectand combined with traditional LDO structure, and finally design out three differentLDO circuits.In chapter3, designed a super source follower LDO structure circuit with a largeexternal capacitance, which insert the buffer to middle stage between the highimpedance of the error amplifier output and the gate of the power transistor withequivalent capacitance to improve the slew rate at power transistor gate. When thecircuit jumps at full load within500ns under a2.2μF external output capacitor, thesimulation and test results show that the maximum overshoot is15mV and40mV inturn.In chapter4, designed a cap-less LDO circuit with dynamic discharging transientenhanced technology, which using active miller compensation to guarantee the loopstability. Load transient simulation show that using this technique, the overshoot ofoutput voltage is reduced from550mV to125mV, the tape-out test results show that themaximum overshoot is only330mV. In chapter5, designed a cap-less or cap-free LDO which can be applied to theSOC internal power supply, the input voltage range is1~1.2V and output voltage is0.8V. The proposed circuit mainly adopts the dynamic bias, trans-conductanceenhancement technology, fast response loop and trans-impedance amplifier error. Inorder to guarantee the stability of the loop, miller compensation is employed.Simulation results show that when the LDO in full load transition within100ns, themaximum overshoot of the output voltage is only141mV, recovery time up to200ns,while the circuit consumes only11μA quiescent current.