The Design Of CMOS Low-dropout Regulator With Fast Load Transient Response

With electronic products such as mobile phone, palm computer develop rapidly, the power management chip play more and more important role in the integrated circuit field. As an important member of the power management chip, linear voltage regulator which has features of low cost, low noise, high precision and simple peripheral circuit is commonly used in integrated system. Because of the changes of market and the rapid development of SoC(System on a Chip), the requirements to LDO(Low Dropout Linear Regulator) chip become more and more rigorous. Lower power consumption, fewer peripheral devices, faster response speed, higher conversion efficiency and power supply rejection ratio have become hotspot of LDO chip.Combing with the hotspot of LDO, the basic principle is analyzied firstly, and then the relathionship between various performance indicators and the circuit architecture is expounded in the chapter two. According to the theory of LDO, three high-performance LDO which are suitable for SoC chip are designed, one of them is about the high PSRR(Power Supply Rejection Ratio) and the other two LDOs are about the load transient response of cap-less LDO. Three LDOs are: 1) a high PSRR LDO using a bandpass feedforward supply ripple rejection circuit. In this LDO, the supply voltage ripple is superimposed on the gate of the power transistor with bandpass feedforward supply ripple rejection circuit, so that the VGS voltage of the power transistor does not contain the power supply voltage ripple signal, thereby the PSRR of the LDO is batter, the PSRR of this LDO can reach-70 dB in the low-frequency band and at 10 MHz frequency the PSRR can achieve-59dB;2) a fast load transient response LDO with slew rate enhancement circuit, which uses slew-rate enhancement technology and dynamic bias techniques to optimize slew rate of the LDO, so the transient response of the output voltage become fast enough when the load current changes, It only consumes 21μA, the LDO in full load transition(100μA~100mA) within 0.5μs, the maximum overshoot voltage of output is only 150 m V and is able to recover within 2μs; 3) a cap-less LDO with high slew rate, the error amplifier of this LDO is a high bandwidth, high-PSRR amplifier, when the load current changes, the error amplifier can export large charging or discharging current to control the gate voltage of the power transistor, thus speeding up the LDO load transient response speed, It only consumes 25μA, the LDO in full load transition(100μA~100mA) within 0.5μs, the maximum overshoot voltage is 190 mV and the maximum undershoot voltage voltage is only 150 m V and is able to recover within 1μs.