Study And Implementation Of ESD Protection Technology For Semiconductor Devices And Integrated Circuits

With the development of semiconductor technology, the research on the reliability of the device is more and more deeply, and the harm of ESD has been paid more attention to. As the need of improvement to the ESD capability of the device is raising, and some devices which meet the requirements of the original standard also need to improve their ESD capability. In this context, the following contents are analyzed and studied:1. Analyze an existing JFET device structure and process; use TCAD tools to establish the structure of the device and the distribution of doping;2. Simulate and get the DC parameters of the device, and compare the difference between the simulation results and actual test data. Use the TCAD tools to simulate the ESD capability of the device, and the results indicate that the ESD capability of the device is larger than 4KV;3. Analyze some samples of the device with ESD failure, and put forward to change the layout of contact layer; add ballast resistance to improve the distribution of ESD current; adjust design rule of metal layer, increase the metal space between Source and Drain to improve the ESD capability of the device between the two electrode; adjust the field oxide process, increase the thickness of Field oxide under Source and Drain electrode to improve ESD breakdown capability of the device that after bonding. In the end, make the ESD capability of the device larger than 4KV;4. Compare and analyze the ESD test method of device, for the lack of ESD test method for a packaged device in time and cost, presents an ESD capability evaluation of simple wafer-level-testing method, and prove that this test method is effective in device development phase.