The Hardware Circuit Design And Implementation Of RFIC Testing Platform Based On FPGA

With the development of wireless communication technology, the performance of radio frequency integrated circuit (RFIC) is becoming more important, in which efficient and reliable test is indispensable. Based on this background and the present researches on IC test, a common RFIC test platform is proposed in this thesis, which consists of device under test (DUT), test board, personal computer (PC) and test instruments.The main work is to complete the test platform hardware circuit design, including FPGA control board design, power supply design and baseband circuit design. The difficulty of this design is that the transmission performance is minimized by the hardware circuit, and guaranteeing the performance of the baseband signal. Baseband signal formed as differential pair connects the DUT with the converter in the test board, where peripheral circuit generates some common mode noise and impact the baseband signal, influencing the reliability of the test platform. The cause of common mode noise is studied at first and then the equivalent impedance network of error of filtering system is modeled and analyzed, which makes a conclusion that mismatch impedance will affect the conversion to differential mode signal of common mode noise. A common mode filter with the balanced structure is designed on the hardware circuit to optimize the baseband signal, which employs the symmetrical filter network. Due to the effects to impedance of PCB line and components parameters, the common mode filter can suppress common mode noise of differential pair furthest, so as to ensure the quality of the baseband signal.Finally, the test platform is verified. According to the measured eye diagram comparison before and after optimization of differential signal, the common mode noise is reduced by 0.12V, and the signal-noise ratio (SNR) of baseband transmission signal in the test platform is improved by 2dB, and the SNR of baseband signal receiving is increased by 3dB. Additionally, the test board can offer multiple adjustable power signals and the current can be measured based on the test results of DUT. The balance conversion time of adjustable IO at dynamic testing is 0.836μs, meeting the design requirement. Besides, the clock amplitude and frequency, the frequency offset and the jitter all reach design specifications.