Design Of A Foldingandinterpolation Analog-to-digital Converter Under 0.18 ?M Technology And Its Test And Verification Platform

With the rapid development of 5G communication system,the requirements on the conversion speed,power consumption and precision of ADC become higher and higher.Folding&Interpolation ADC has high conversion speed,moderate accuracy and power consumption,small area,and has a great application prospect in high speed communication system.In this paper,the performance of analog-to-digital converters are analyzed and the analog digital converter with Folding&Interpolation structure is introduced in detail.Then the specific implementation methods of each part of the circuit are promoted.At the same time the overall structure and its simulation data are given.Meanwhile this paper uses the two-stage pipelined main sample and hold circuit,by increasing the sample rate,linearity and hold time,the maximum sampling rate and the maximum resolution of the analog to digital converter are improved.A two-stage cascade folding and interpolating structure is also used in the realization of large folding and interpolating factor while maintaining circuit high bandwidth.The front-end analog circuit offset has also been optimized by adding resistor-mean network to the pre-amplifier circuit array to reduce the offset in the circuit.In addition,by using two channels co-coding,the size of the circuit is reduced and the synchronization of the two channels is ensured.The layout of the whole system is completed,the chip area is 1.5×1.4mm2.After extracting the parasitic parameters of the layout,when the input signal frequency is Nyquist frequency and the sampling rate is 1GSps,the simulation results show that the SNDR can achieve 45dB,SFDR can achieve 59dB and ENOB can achieve 7.2bit.At the same time,a chip test and verification platform for an 1GSps,8bits resolution high speed ADC is designed.The platform is used for testing a Folding&Interpolating ADC chip which has been designed and taped out by our research group.Its hardware can be divided into two parts:ADC chip test board and FPGA data acquisition board.In the ADC chip test board,the input analog signal is converted from the single ended signal into a differential signal by the balun chip,at the same time,the 10MHz reference frequency is multiplied to generate required sampling clock signal by the wideband synthesizer chip ADF4350.The input data is converted by the Folding&Interpolating analog-to-digital converter chip,then is converted into the 8 LVDS differential signals by LVDS conversion chip.After being sent to the high speed interface,the output signals are sent to the FPGA data acquisition board.In the FPGA data acquisition board,the ADC data firstly is obtained by FPGA through the interface,then is processed in the way of delaying,sampling,storaging,displaying and so on by internal circuit module like IBUFDS,IDDR etc.The ADC output data is displayed by the Chipscope tools which are provided by ISE software platform in order to quickly adjust the test conditions and verify the performance of the chip.The data from the test result shows that,in the 44MHz input signal,360MHz sampling frequency,SFDR is 35dB,ENOB is 5bit and SNDR is 33dB.