Research And Design Of RF Front-End For Ultral-Wideband Transmitter

This paper outlines the development and research status of UWB technology, points out the advantages of UWB through comparing the advantages and disadvantages of different short distance wireless communi-cation technologies. After analysis the basic structure, main indexes and the problems maybe appear in design process of the existing UWB transmitter, the Zero-IF architecture is adopted in the transmitter front-end chip. It consists of three parts:the low-pass filter, the up-mixer, and the driver amplifier. The low-pass filter is achieved through simple third-order RC filter. The top-down design method is adopted in this work, firstly made sure the performance index of the whole chip, then the index is assigned to each module. In order to debug conveniently and verify the performance of the whole chip, driver amplifier was taped-out separately.The main function of the up-mixer is to complete the frequency conversion, and it’s one of the important modules in the transmit chain. On the basis requirement of indicators, the whole difference I/Q quadrature modulation structure is adopted in up-mixer. It includes two Gilbert double-balanced mixers and a center tapped differential inductor which is used to as the output load. Inductance load can expand the bandwidth of the mixer and provide better broadband performance. The value of the inductance needs to consider the driving amplifier input capacitance and the parasitic capacitance of the line, then the resonant frequency should be set in the desired frequency.The full differential cascode driver amplifier structure is adopted in this paper, and in order to cooperate better with receiver, the power gain is set to adjustable model.16 different power gains are achieved by controlling the bias current. The linearity of DA is the key point in this design, especially the output ldB compression point. Under the condition of 1.2V low voltage power supply, it’s necessary to reduce the transistor layers to gain a greater output swing. The chip designed in this paper need to be tested in PCB through bondwire, so the design of matching in output is discussed detailed. The optimization of performance in output matching of PCB board can be realized by Co-simulation which is a DynamicLink between ADS and Cadence.The transmitter front-end chip designed in this paper is achieved in TSMC 0.13um CMOS process, the area of the whole chip is 1.084 x 0.795mm2. The chip is tested on the PCB board. The output ldB compres-sion is 5.7 dBm@6.8GHz, slightly below the index requirement, one main reason is the output match of the PCB board needs to be further optimized. The OIP3 is 8.42 dBm@6.71 GHz and IIP3 is 2.64 dBm@6.71 GHz. The maximum power gain is 5.8 dB, and the gain range is 0 to 5.8dB.The total current of the PCB test board Is 22 mA.