Oriented Applications Of Satellite Navigation Terminal Transmitter Rf Front-end Chip Design

This project is originated from the subject Wireless Communication Core Chips, which is a part of industry development project Filed-Faced Core Chips Design and Industrialization of Department of Science and Technology, Guangdong province. Deeply research on ISM band CMOS/BiCMOS based fully integrated transceiver chip design techniques is done in this thesis. An L band transmitter RF front-end chip including low pass filter,modulator (up conversion mixer),VGA and driver amplifier, which is used for satellite navigation terminal, is designed in this paper. The specifications of every module are derived from Chinese Beidou satellite navigation system transmitter requirement under the conditions of high integrity, low power and some design margin left. Then, every module and the RF front-end chip are implemented in BiCMOS process.The fourth order Chebychev LPF with an on-chip RC tuning circuit is designed using Thomas-Tow active RC filter structure. It could tune BW-1dB variation up to±30% through off-chip 5bits digital signals, which is caused by process corner variation. The LPF is power-saving, only consumpting about 2mA current, whose out-of-band rejection performance is well, achieving more than 38dB rejection at 12.24MHz.The high linearization modulator (up conversion mixer) based on the refined double balanced Gilbert-cell structure, uses two source-coupled pair as tranconductor input stage, LC tank as load. With about 10mA current consumption, it achieves more than 55dB IM3 rejection and 50dB LO rejection.With the use of control signal convert circuit and temperature compensation techniques, the disadvantage deviated from linear-in-dB at high gain of signal-summing VGA is solved, and a 20dB liner-in-dB range signal-summing VGA is realized. Driver amplifier which is consisted of NPN differential pair with its emitter connected to differential inductor achieves the trade-off between gain and linearity, and lowers the effect to circuit performance caused by bonding wire parasite inductor. The amplified differential signal is converted to single end signal through on-chip balun, and then matched to off-chip 50? load through LC matching circuit.The transmitter RF front-end chip designed in this paper uses directly up conversion architecture, its structure is simple and highly integrated. The chip is implemented in Jazz SiGe 0.35μm 1P4M BiCMOS process. The chip consumes about 220mW, under conditions of typical process corner, 3.3V working voltage and 60℃working temperature. The simulation results shows that output power is more than 5dBm, output 1dB compression point is more than 10dBm, LO rejection is more than 40dB, and IM3 rejection is more than 30dB.