Improvement And Performance Analysis Of LDPC Decoding System Based On Sum-product Algorithm

Presently communication has become one of the most important needs for humans andone of the most attractive areas for investment and growth. There has been a lot oftechnological advancement in different areas of human endeavor, but there are still lots ofclassic technology that need improvement to increase benefits and reduce cost byreducing complexity and enhancing performance.Low-density parity check (LDPC) codes have been shown to have near Shannon limitperformance for error correction in communication systems. However, compared to othererror correction codes, encoding and decoding LDPC codes always require considerablepower and processing time which would limit their practical use. Nowadays reducingcomplexity, embedding subsystem in communication systems and electronic systemspeed growth is a serious concern. The limit of the hardware level speed pushes theenhancement and replacement of algorithms, a field that many researchers are workingon. Enhancing algorithms to reduce hardware level complexity is an intelligent andreasonable choice that can in some case give the ability to downgrade hardware level toreduce cost. In this thesis, the following techniques are proposed for LDPC decodingsystems:Firstly, as the LDPC decoder using an iterative decoding algorithm is complicated, itis necessary to reduce the number of calculations to achieve a better decoding speed andpower saving for the decoder. So that a new algorithm based on Sum-product algorithm(SPA) for processing LDPC algorithms using stopping node is proposed in this thesis.This is the intelligent way of predicting that reduces the computing complexity thatenhances speed and hardware level constraints, complexity and technology involved. Thecomputational complexity factor of new algorithm has been also introduced in evaluatingthe complexity of decoding calculations. In the proposed algorithm, we show how tomake early decisions to reduce calculation of the next iteration and how to remove theeffect of short cycles. The simulation results demonstrate that the proposed algorithmwas able to reduce the number of iterations, speeds up decoding process, simplify thecoding scheme while maintaining processing quality where losses are insignificant andacceptable.Next, we propose a new LDPC decoding algorithm using the free bit which canachieve enhanced Bit Error Ratio (BER) performance. In the algorithm, the re-decodingLDPC is presented to reduce the number of error bits with common decoding based on the characteristics of free bits. The simulation results confirm that BER performance ofthis algorithm is improved significantly compared with conventional sum productalgorithm.Finally, the study investigates a simplified LDPC decoding by calculating approximateLog-likelihood Ratio (LLR) in non-coherent BFSK systems and extends it to the case ofmultiple MFSK. Combining the sub-optimal LLR method and stopping node algorithmcan make a breakthrough in decoding speeds. Simulation results demonstrate that thenew proposed methods can reduce a great number of calculations which will lead toinsignificant quality decreasing. As a result, the processing time of LDPC decodingalgorithm is speed up but keeping the same algorithm qualities and enhancedperformance.