| With the development of complement-metal-oxide-semiconductor (CMOS) technology, silicon (Si)-based metal-oxide-semiconductor devices have almost reached their physical and technical limitations and thus, it is difficult to meet the demand in device scaling down. Germanium (Ge) and III-V semiconductor and some other high mobility materials have been paid great attention as a promising candidate for channel material because of their high mobility. Co-integrating high performance Ge-based pMOSFETs and III-V nMOSFETs on Si substrate is regarded as one of the best ways to realize high performance CMOS in "more Moore" time. However, high quality high-k/Ge interface and hetero-integration of Ge on Si platform are considered as the fundamental issues for improving the performance of next generation CMOS devices. In this thesis, Ge-MOS interface control, optimization of gate dielectric, fabrication process and characterization of Ge MOS device and co-integration of Ge-based MOS on Si substrate are systematically discussed and investigated. The main research contents of this dissertation are as follows:First, an atomic layer deposition (ALD) in-situ single ozone oxidation method (SOO) with ultrathin Al2O3 capping layer is proposed for fabrication of high quality GeOx interface layer in a low temperature case. In this study, deposition of ultrathin Al2O3 capping layer was performed before forming GeOx interface layer by ALD in-situ ozone oxidation that can both control effectively the oxidation reaction and avoid possible damage to GeOx interface layer in the following high-k depositon process. Then, high quality Al2O3/GeOx/Ge MOS capacitors with ultrathin GeOx interface layer are fabricated at a process temperature not higher than 400℃ (GeOx interface layer was formed at 300℃).In an attempt to improve the quality of high-k dielectrics, ALD in-situ cycling ozone oxidation (COO) method is proposed based on the study of SOO process. The Ge/high-k interface and high-k dielectric quality were further improved with COO treatment process. The lower interface state density (Dit) was obtained without increasing the thickness of GeOx interface layer. Furthermore, mechanism of the improvement was systematically investigated t with X-ray photoelectron spectroscopy (XPS) and spectroscopy ellipsometer (SE) analysis from the viewpoints of band alignment, sub-gap state absorption and the defects in Al2O3.Based on our understanding about Al2O3/Ge interface and Al2O3 dielectric quality in SOO and COO capacitors, the high performance Ge pMOSFETs were demonstrated with Al2O3/GeOx/Ge gate stacks. Meanwhile, the electrical performance of Ge MOSFETs fabricated using SOO and COO method is comparatively studied.In order to realize high performance CMOS on Si substrate, the integration issue of Ge-based MOS on Si platform was further investigated. Reduced pressure chemical vapor deposition (RPCVD) system was employed for Ge epi-growth on Si platform. To form high quality Ge epitaxial layer, a high-low temperature two-step deposition process was used. Based on the results on Ge MOS devices, Si-based Ge (100) pMOSFETs was fabricated using SOO method as well as improved n-well ion implantation process. Experimental results demonstrated that Al2O3/Ge-on-Si interface was well passivated with a Dit near the mid-gap of～5×1011 eV1-cm-2. Moreover, a current on-off ratio of Ion/Iiff=104 and a subthreshold swing of SS = 120mV/dec for the Si-based Ge (100) pMOSFET were achieved by single ozone oxidation method. The effective mobility is extracted by split C-V method, and the hole mobility peak reached 524 cm2/V·s. Finally, the impact of scattering mechanism on device channel mobility is discussed and investigated. It was proposed that further enhancing the mobility at high electrical field and reducing the channel defects by optimizing the epitaxy technique and replacing the n-well formation process from implantation to gas-phase doping may be an effective way to achieve better performance for Si-based Ge devices. |
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