Based On High K Gate Dielectric Ⅲ - Ⅴ Compound Semiconductor Mos Device Research

Si-based CMOS technology has been successfully scaling down for decades to meet Moore’s law. With higher operating frequency and larger integration density in a single chip, the power density is becoming a more and more serious issue. Therefore, power constraints are the major concern for future transistor engineering. Since power density is proportional to the operating voltage squared, material with higher carrier mobility or velocity can be applied to obtain the high performance under low operating voltage, using reduced power. Among all those non-Si CMOS technologies Ⅲ-Ⅴ materials are the promising solutions. The research of Ⅲ-Ⅴ CMOS technology is believed to be very practical for the industry application.The development history of Ⅲ-Ⅴ technology is traced back. Actually, the history of Ⅲ-Ⅴ technology is mainly the development process of gate dielectrics. It had been a problem of growing high-quality gate dielectric on Ⅲ-Ⅴ surface until ALD high-k technology was applied. In some degree, ALD high-k technology is considered to be the key progress in Ⅲ-Ⅴ technology development history. The development of theory model, especially the model of interface between gate dielectric and semiconductor is also investigated.The most compete topic-high-k/InGaAs system is focused as the beginning of this thesis. After widely investigation, the main problems on the high-k/InGaAs are found to be the frequency dispersion in accumulation region and the current hysterysis. To exploring these problems, the extended fast Id-Vg methodology is proposed to apply the traditional fast Id-Vg method to high frequency and large device characterization. Three problems are solved, including the impedance match in high frequency circuits, the displacement current signal of large device and the power-droop effect in high frequency circuits. The high-performance enhancement-mode n-channel InxGai-xAs MOSFETs with atomic-layer-deposited Al2O3as gate dielectric are demonstrated by Purdue University. A0.4um gate-length MOSFET with an Al2O3gate oxide thickness of10nm shows a maximum drain current of1.05A/mm at gate bias of4V, drain voltage of2V. Finally, a fast oxide trap response of5ns can be probed on a2um gate-length InxGa1-xAs NMOSFET devices with a15%larger intrinsic current than DC current. After measurements and analysis, the high-k oxide trap density of3.43×1018cm-3is calculated on III-V, which is lower than most high-k reported results. Therefore, the high performance of ALD Al2O3/InGaAs NMOSFET can also be proved.Inspired by the Fermi-level unpinning on GaAs(111)A surface, inversion n-channel metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Al2O3as gate dielectric are fabricated on two crystalline surfaces:InP(111)A and InP(100). A record high drain current of600uA/um is obtained on InP(111)A surface at Vgs=Vds=3V with a gate length of1um and Al2O3dielectric thickness of8nm. The maximum drain current is greater by a factor of3.5on the InP(111)A surface compared to devices fabricated on the InP(100) surface at the same bias conditions. During room temperature positive gate stress,"zero" drain current drift is observed for InP(111)A devices, in great contrast to InP(100) devices. The greater maximum drain current and the "zero" drain current drift on InP(111)A can be explained by oxide band bending caused by charge neutral level shifts and lower border trap density. This Charge Neutral level shift model can also be extended to different crystalline surfaces on InGaAs and GaAs. In order to further understand the drain current drift mechanism in InP NMOSFETs, similar measurements are carried out at elevated temperatures, ranging from25to175℃. Okamura’s two-trap-level model is used to quantitatively describe the temperature dependent current drift. After the simulated current drift data coinciding with measured data, the border trap energy level and concentration in ALD Al2O3on the InP(111)A surface are determined to be～68meV above the conduction band bottom and1.7×1019cm-3.Most low bandgap Ⅲ-Ⅴ materials are of great interest since they have even higher electron mobility. However, the traditional CV and conductance method can’t properly characterize their interface anymore. Therefore, temperature related CV and conductance method is used to characterize the interfaces between high-k/InAs and high-k/InSb. The CV/GV measurements can be operated at temperature low to10K on self-built measurement platform. The Fermi-level movements on Ⅲ-Ⅴ surface can be traced through temperature related CV/GV measurements. Because the minority response at room temperature is suppressed at77K on ALD Al2O3/InSb, clean accumulation, depletion and inversion features like standard SiO2/Si interface are observed. The conductance method shows a mig-gap interface trap density4.14×1012/cm2-eV. To further improve the conclusion on different crystalline surface among Ⅲ-V materials, similar experiments are carried out at temperature down above50K. At50K, the Fermi-level is found to be partly pinned on InAs(100) surface, while sharp CV modulation is observed on InAs(111)A and its interface trap density is2.42×1012/cm2-eV.The above all focuses on n-channel Ⅲ-Ⅴ material studies. From the consideration of Ⅲ-Ⅴ CMOS configuration, the studies on p-channel Ⅲ-Ⅴ materials are also of great importance. However, due to the poor hole carrier transportation on most Ⅲ-Ⅴ materials, less research work are talked about it.From the good hole mobility and charge neutral level model analysis, GaSb materials have been chosen as suitable Ⅲ-Ⅴ p-channel materials. For a MOSFET device with gate length of0.75um, a maximum drive current of70mA/mm has been achieved when gate bias is-4V and drain bias is-3V. The off-state current has been significantly reduced with process optimization by lowering the thermal budget. By comparing the interface trap density under different process conditions, process optimization is verified by the quantitative interface progress. To further decrease the equivalent oxide thickness, an interface characterization of p-type GaSb MOS structure has been performed with ALD Al-first and Hf-first HfAlO gate dielectrics. The Al-first process is found to improve the characteristic of high-k/GaSb MOS such as breakdown strength, frequency dispersion in accumulation region and gate dependent capacitance modulation. From distributed border trap model and temperature dependent conductance method, the border trap density (Nbt) inside high-k dielectrics and its interface trap (Dit) density can be extracted for samples under four process conditions. The Al-first HfAlO/GaSb with PDA shows the smallest Nbt4.5×1019cm"3with a barrier height of2.75eV below the valence band edge of GaSb. However, the Al-first HfAlO/GaSb without PDA is extracted with the smallest D;t of4×1012cm-2eV-1near the valence band edge. These Dit distribution and border trap density Nbt accurately explains the CV characteristics of HfAlO/GaSb MOS capacitors. The PDA process on HfAlO/GaSb system is found to allow a tradeoff between interface quality and border trap density which requires further study and optimization.Based on the summary of this research, future problems and development trend are estimated for Ⅲ-Ⅴ technologies.