Based On Three Key Technologies Of Multicore Systems Triba Storage System Study

Due to the low design complexity, high clock frequency, and high throughput, Chip Multi-Processors (CMP) becomes the mainstream of processor development technologies. CMP improves system performance by exploiting processor architecture. The key to design CMP is to construct efficient communication architecture and fast data storage path, for CMP structure improves system performance by the corporation among cores which can exploit the parallelism at different granularity.Triplet Based architecture (TriBA) aims on efficiently supporting object-oriented technology by specific CMP architecture and micro processor architecture, so to improve system performance by shrinking the gap between processor developing technology and software developing technology. This thesis researches the key technologies of TriBA based CMP memory architecture,that is to propose the shared multi-channel on-chip memory architecture (SMC-OCM) of TriBA, and to research the key technologies of implementing this architecture.TriBA based SMC-OCM architecture is a kind of shared memory CMP architecture, the sharable memories in SMC-OCM are consisted of multi-channel on-chip memory and L2 Cache. SMC-OCM architecture aims on increasing the system real-time response performance, supports sustained efficient parallel communication among cores, supplies parallel data transmission and sharing, and satisfies the real-time performance requirements of embedded applications.We designed the sharable multi-channel on-chip memory (MC-OCM) according to the performance targets of TriBA based SMC-OCM architecture,and implemented the multi-channel on-chip memory controller based on FPGA. The multi-channel feature of the sharable on-chip memory can decrease parallel access conflicts and increase the parallel data transmission bandth; multi-body overlapping interconnection mode of SRAM array supports parallel pipeline data transmission among cores; hardware based synchronization scheme further decreases the communication delay; the space management strategies of the sharable multi-channel on-chip memory optimizes the shared memory space utilization and further improves the response performance of the whole memory system; performance testing and analyses of MC-OCM was carried out, the results showed that the designed MC-OCM is performance efficient in terms of hardware cost, parallel data transmission efficiency and power.We constructed the VHDL system of SMC-OCM based on LEON3 processor utilizing the designed multi-channel on-chip memory. Performance simulation and testing of SMC-OCM is processing on the VHDL system. The simulating results showed that SMC-OCM is performance efficient compared to the state-of-the-art and traditional shared Cache architecture.The independent data channel organization of on-chip memoey in SMC-OCM increases the wire density in VLSI layout,which will affect the signal transmission reliability. So a self-adaptive dynamic BUS encoding scheme is proposed in this thesis. The scheme supplies self-shielding for low significant bits of address BUS which with high information entropy. So the BUS encoding scheme can decrease the coupled interference among wires and can enhance the signal integrity , further improves the signal transmission reliability. The proposed encoding scheme achieves high shielding degree without additional hardware cost and without decreasing of program executing performance.