Research And Design Of HEVC Bitstream Parsing And Entropy Decoding Module

With the improvement of the computing perfomance, digital video technology has been developing faster and faster. It has an urgent demand for the standard with higher resolution, frame rate, compression ratio, stability and strong network adaptability. However, the widely used H.264 standard, because of its limit in compression ratio, can not well match the requirements. In this case, High Efficiency Video Coding (HEVC) is proposed to sovle the above problem.As the latest digital video coding standard, there are innovations in HEVC hybrid video codec framework, such as block processing, prediction and entropy coding. It offers flexible picture division method, more intra predition mode, competition based motion vector prediction, tile splitting and wavefront parallel processing. The above technologies help HEVC decrease the bitrate of 50%, comparing to H.264. Considering that high performance means high cost, HEVC needs higher processing ability for software codec. So, it is important to research and design a specific HEVC codec IP. This thesis researches and solves the problem by the following steps:1) Research HEVC standard and arithmetic. Analyze the definitions and features of defferent levels, compare them with h.264 and get the result of coding complexity and efficiency.2) Design hardware architecture of the decoder based on the analyzing results. Propose the bitstream ring buffer to increase the parallel decoding rate; propose the parser FSM tree to control the parsing process in order; propose the fast renormalization structure to improve the decoding efficiency of syntax elements decoding.3) Simulate the decoder. Set up the simulation environment and the FPGA verification platform, test the hardware decoder with standard testing bitstream in main tier. The result shows that the decoder design in this paper can decode the bitstreams correctly and achieve the Level 4 main tier in HEVC standard.In summary, a hardware accelerating module for HEVC decoding problems is proposed and designed in this thesis, which offers new solutions and methods of hardware design in performance improvement and parallel computation.