Font Size: a A A

Research And Verification Of OpenSPARC T1 Processor Storage Mechanism

Posted on:2017-01-29Degree:MasterType:Thesis
Country:ChinaCandidate:Z J HouFull Text:PDF
GTID:2308330488495483Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
With the continuous development of microelectronics technology machining, Moore’s Law continues to be verified.lt has been difficult to adapt to many applications for traditional single-core processors to meet its performance requirements,multi-core and multithreading porocessors are coming to our sight.As we know, Cache is the crucial component of an inside multi-core multi-threaded processor chip,whose performance have an essential impact on the intact performance of the processor.Thus,an 64-bit CMT processor called OpenSPARC T1 designed by Sun corporation is chosen to implement some reseaches to the working mechanism optimizing strategies, and Evaluation Tool of the cache, and designed OpenCache which is a teaching platform for undergraduate assisted learning.This paper introduces the current development trend of the microprocessor and its related technologies, especially the working mechanism of cache. According to the open OpenSPARC T1 source code, we analyze the architecture of the processor. Then in this paper, we deeply study the cache and data interaction mechanism of OpenSPARC T1 processor, aiming at three fundimental indicators:the miss rate, the miss penalty and the hitting time of cache.we analyze 6 cache optimizing technologies implemented on the optimizing OpenSPARC T1 processor. As a result, we verify the fruits by SimpleScalar simulator. On this basis, we explore the solution of OpenSPARC T1 processor cache vibration. We use a combination of hardware and software optimization technology Space Lock Loop, and we calculate the theoretical value of the benefits of this technology to enhance the OpenSPARC T1 processor system performance.Finally, this paper presents OpenCache teaching platfor, which is used for undergraduate teaching. OpenCache is based on OpenSPARC T1 processor hardware platform, its design comes from the open source simulator SimpleScalar. We analyze OpenCache design requirements, summarized the main points of design should pay attention, according to the OpenSPARC T1 processor RTL source code, we use EDA tools to build a simulation environment, carried out regression testing. According to the teaching needs, the platform designed eight functional systems, and introduces the implementation process.By OpenCache teaching platform; students can more deeply understand and master the modern computer Cache technology.
Keywords/Search Tags:OpenSPARC T1, Cache, Optimization, Space Lock Loop, Teaching Platfor
PDF Full Text Request
Related items