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Design Of Transmitter Chain For C-band Transceiver System

Posted on:2017-05-18Degree:MasterType:Thesis
Country:ChinaCandidate:X L WangFull Text:PDF
GTID:2308330488457865Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Active electronically scanned array (AESA) technology has been applied in various military devices because of many advantages of AESA. It is vital to control the size, weight and cost of each T/R module since there are thousands of T/R modules in AESA. Multi-function chip (MFC) is a technical solution for next generation T/R modules. The development of science, especially in various manufacturing technique (CMOS/SiGe), makes it possible for the realization of highly integrated, low-cost multi-function chip.This paper presents the circuit design of transmitter chain for C-band transceiver system in 0.18μm RF CMOS technology. This transmitter chain uses the Hartley architecture and consists of five modules which are IF amplifier, VGA, ±45° phase shifter, up-conversion mixer and PA. It can convert IF signal into RF signal and implement sum-frequency rejection. The IF amplifier uses capacitance cross coupling technology to achieve a higher gain and better performance. VGA is implemented by linear region cascade for wider bandwidth. A two stage polyphase filter is used as ±45° phase shifter to implement the conversion from differential signal to quadrature differential signal. The quadrature up-conversion mixer is based on Gilbert active double-balanced structure for better sum-frequency rejection. The PA with CSCG structure biased in class AB for better reverse isolation and promotes the stability by using RC feedback circuits. This paper presents circuit design and layout design of the transmitter chain. The post-simulation results show that under 3.3V power supply, TT corner and 27℃, the conversion gain is 29.63dB, OP1dB is 11.22dBm, sum-frequency rejection is more than 57.81dBc, the S11 of IF ports is less than-27.41dB, the S22 of RF ports is less than-16.03dB, the LO-IF port isolation is greater than 73.98dBc and the LO-RF port isolation is greater than 29.71dBc.The transmitter chain has the advantages of low VSWR at input and output ports and high linearity. The post-simulation results can satisfy the system requirements and the transmitter chain proposed in this paper can be applied in C-band transceiver system.
Keywords/Search Tags:Transmitter chain, Hartley architecture, High integration
PDF Full Text Request
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