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Design Of C-band Transmitter Front-end

Posted on:2016-12-07Degree:MasterType:Thesis
Country:ChinaCandidate:T L SunFull Text:PDF
GTID:2308330503976370Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
Phased Array system with Active electronically scanned Array (AESA) technology is widely used in space surveillance, missile defense, and satellite communications etc., including military and civil areas. High integration, low cost and multi-function of RF front-end chip is one of the important technical ways to address these needs. With the development of silicon RF integrated circuit technology, digital logic is used to process compatible with CMOS technology to realize RF front-end chip is one of the important trends of the AESA integration development.This paper introduces several common-used transmitter structures and focuses on the Hartley sum-frequency rejection transmitter implemented in the C-band transceiver system. The transmitter front-end presented in this paper is designed in 0. 18∑m RF CMOS process, including up-mixer, active LC-balun, RF power amplifier, LO-SDC, ±45 ° phase shifter and LO-driver. On the basis of Gilbert double balanced mixer, the orthogonal complex mixer is designed to realize the function of sum-frequency rejection. The active LC-balun is used to convert the differential signal to single-ended signal. The design and implementation of AB-class power amplifier is proposed based on one-stage cascode topology to enhance the reverse isolation and promote the stability by using RC feedback circuits. In the part of LO-SDC, the Common Source-Common Gate (CSCG) SDC using capacitor cross coupling (CCC) technology is proposed. The design of ±45° phase shifter is based on PPF to convert differential LO signal to orthogonal differential signal. The post-simulation results show that on the supply of 3.3V power, TT comer and 27℃, the current consumption is 136.95mA, the conversion gain is 17.26dB, OPldB is 12.09dBm, sum-frequency rejection is more than 46.38dBc, the S22 of RF ports is less than-18.36dB, the S33 of LO ports is less than -19.16dB and the LO-RF port isolation is greater than 28.76dBc.The post-simulation results satisfy the system requirements and the transmitter front-end proposed in this paper can be applied in C-band transceiver chip.
Keywords/Search Tags:Hartley transmitter, transmitter front-end, sum-frequency rejection
PDF Full Text Request
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