Hardware Implementation And Verification Of Matrix Inversion Based On LU Decomposition

Matrix operations are basic scientific and engineering computing, which are widely used in digital signal processing and image processing. Due to the high real-time requirements of those applications, it is required to use hardware implementation method to accelerate the speed of matrix operations. The matrix inversion is one of the most important and difficult operations of matrix operations, whose execution speed has a significant impact on the efficiency of the entire system. Since most existing hardware implementations of matrix inversion have at least one of the defects such as large complexity of hardware resources, big requirement of storage resources, only applied for low order of matrix inversion and so on, this paper presents an hardware implementation method of matrix inversion based on LU decomposition. This method designs three modules based on simple arithmetic operation units to complete the matrix inversion calculation. Each module is achieved by the way of reconfiguration, saving more than 50% of the hardware resources. Besides, parallelization methods are designed for each module, which effectively improves calculation efficiency and hardware resource utilization.With the rapid development of SoC design techniques following the Moore’s Law, the rapid expansion of the chip size of function led to rapid growth of verification complexity. Nowadays validation work has accounted for about 70% of the entire chip development, so verification efficiency is increasingly becoming the bottleneck of the design efficiency. The traditional verification methods have been unable to meet the complex chip design verification. Thus, this paper uses UVM (Universal Verification Methodology) which is the latest verification technique, to verify the matrix inversion design. This paper builds an efficient, highly automated, reusable verification platform, which greatly improves the verification efficiency. By the way of random generation of stimulation combined with randomized constraints, a large number of desired testing data can be generated, and the coverage of functional requirements can quickly achieve 100%, ensuring the functional accuracy of the designed module. Meanwhile, the performance of the designed module is analyzed according to the calculation accuracy statistics and the run time statistics. Finally, we can get complete verification results for the matrix inversion module design.