Design Optimization And Modeling Of High Power RF LDMOS Transistor

Lateral double diffused metal oxide semiconductor(LDMOS) transistor has basically replaced bipolar devices and become the mainstream technology in the radio frequency(RF) field because of its all kinds of advantages. Due to the huge profit margins and important military applications, RF LDMOS has become a research hotspot of the semiconductor industry, our country has already invested in the research and development of RF LDMOS.The target of this design is to obtain a RF LDMOS with high power, which adopts a backside source structure with double source field plates. By the use of semiconductor simulation software to optimize the structure and impurity dose, to make the device has excellent DC and frequency characteristics, then the layout of the device according to the structure optimized before was designed, and NEC finished the tapeout experiment finally. The DC test results of the transistor with the gate width of 200μm show that the transistor has 100 V breakdown voltage, 180μA/μm saturation current density and 2.2V threshold voltage. The packaging device provides a maximum output power of 500 W, with the efficiency and power gain of 45% and 18 dB respectively, which meet the design requirements.We have also tried to model the device with small signal in this thesis, parasitic and intrinsic parameters of the small signal model equivalent circuit have been obtained, Advanced Design System was used to optimize these parameters to make the model more precisely. The significance and the common process of the large signal modeling was discussed, with a large signal modeling method being introduced.