Research And Design Of Dual Channel 2 Gbps Data Receiver For MIPID-PHY

There are lots of chips in the mobile device with many complex interfaces. Such as the internal camera interface, display interface, RF-baseband interface. MIPI(Mobile Industry Processor Interface) is an open standard for mobile application processors initiated by MIPI alliance, which is meant to enhance the consistency of the application processor interface, and to promote the reuse and compatibility of mobile devices.As a sub project of AM-OLED display driver chip, this paper introduces the basic concept of MIPI D-PHY and the electrical characteristics of the modules in serial receiver as well as the basic architecture of this design. In high-speed mode, the characteristics of traditional bandwidth expansion technique is analyzed. Based on the requirement of the high speed, low power consumption and small area occupied, this paper provides a new type of active inductor and a complete design method of the high bandwidth amplifier in the serial receiver. Compared with the general design, the bandwidth of the amplifier is greatly improved. The design and simulation of dual channel with 2Gbps data transmission rate are completed. At the same time, the transmitter, receiver and contention detector which are applied in low-power mode are designed. The transmitter is designed to meet the requirement of the slew rate at different load capacitances. Refer to low power receiver and contention detector, make full use of the feature that both of them shall filter out noise pulses and RF interference, then distinguish the different requirements of threshold voltage, and this paper provides improved hysteresis comparators to fulfill the requirements.The project is designed with 90 nm CMOS process. The circuit design of analog part of D-PHY is completed. Pre-simulation, layout and post-simulation are conducted. Then tape out and test the chip of the first version. In the low power mode, the transmitter, receiver and the contention detector achieve design request. And pre-simulation, postsimulation and test results meet the D-PHY specification. In the high-speed mode, the results show that the data transmission rate of dual channel can reach 2Gbps in presimulation and post-simulation, which is 1.04 Gbps in chip test. This paper also presents the analysis of the cause why test results below the standard, and provides the improvement method.