Study Of Continuous-time And Discrete- Time Hybrid ΣΔ ADC Based On Digital Noise Coupling Technique

With the rapid growth of communications and multimedia market, digitization has become a trend. More and more analog processing technologies have been replaced by digital processing technologies. As a bridge between the analog and digital world, analog to digital converter (ADC) has been widely used in various electronic devices. Adopting the strategy that improves the resolution at the cost of slow speed and comb-ing oversampling and quantization noise shaping techniques, ∑Δ ADC achieves high resolution. Thus, ∑Δ ADC is the preferred architecture in the system with high ac-curacy requirement such as communication system, measurement system, high-quality audio system and so on. In spite of the advantage of high resolution, ∑Δ ADC faces the problem of high power consumption. Especially for the increasingly stringent require-ments of low-power products, this problem becomes more serious. It is of necessity to meet the requirement of both high resolution and low power. Power saving can be done in many ways. Among the various low-power solutions, applying continuous-time sys-tem and increasing the resolution of the quantizer have widely been selected. However, there are some limitations in the two solutions.In order to break limitations of the two above mentioned solutions, the continuous-time and discrete-time hybrid ∑Δ ADC based on digital noise coupling technique is proposed. Continuous-time and discrete-time hybrid structure not only maintains the advantages of low power consumption, but also overcomes the difficulties of inaccu-rate coefficients and complicated design in continuous-time structure. Applying digital noise coupling technique, the system can increase the bits of quantizer without suffer-ing from the exponential growth of the dynamic element matching (DEM) logic. At the same time, the switch capacitor compensation method is proposed to solve the problem of gain loss due to sampling in hybrid structure.According to the above research methods, the proposed architecture is analyzed and verified by two aspects. On one hand, through the analysis and calculation, the specific architecture model is determined. Behavioral simulations is performed to ver-ify the effectiveness of the proposed technique. Meanwhile, in order to provide the basis for circuit implementation, nonidealities including finite gain bandwidth product (GBW), slew rate, integrator leakage, digital to analog converter (DAC) nonideality, the nonideality of digital noise coupling technique and so on is analyzed. On the other hand, the system circuit is designed and verified according to the above analysis. The proto-type is fabricated under SIMC 0.18μm standard complementary metal oxide semi-conductors (CMOS) technology. The first continue-time integrator adopts the simple circuit and the low power RC structure. The switch capacitor structure with high pre-cision and good linearity is used in the second integrator. The DEM circuit is realized by data weighted averaging (DWA). The quantizer with noise shaping is implemented by moderate accuracy and low power successive approximation register (SAR) ADC. Finally the circuit achieves the expected goal and its performance is consistent with re-sults of behavioral simulation.