Development Of High-speed Demodulator

At the beginning of this article, the research and development situationat home and abroad of high-speed demodulator is first introduced. Secondly, the key technologies of high-speed demodulator which includeparallel digital down conversion, matched filtering, clock recovery, carrier recovery, equalization and error correction are illustrated. Circuit model is constructed according to detailed formula reduction and simplification. And then, a detailed design of the circuit is demonstrated. The performance analysis of FPGA, ADC and analog front-end which are used by the design is presented. Finally, A full functionality prototype is finished and the performance of it is also presented.High-speed demodulator is the core equipment in satellite ground receiving system which is used to receive high speed down link signals from high resolution satellites and airplanes. The demodulator designed in this article supports dual-channel demodulation. The processing speed of each channel is 1Gbps and co-processing of dual-channel is also supported. Base on the works in this article, the key technologies of high-speed demodulator are achieved and gap distance between our country and other developed countries is shortened. The high-speed demodulator has wild application prospect in high resolution remote sensingsatellite systems and communication satellite systems. It can also be used in high-speed wireless networks and military respects.