The Design Of 1.5-3.0GHz Charge Pump Phase Locked Loop Based On 40nm CMOS

Since the 21st century, with the increasing needs of communication, new communication techniques and the implementation have been developing. With the improvement of people’s living standard, the development of wireless communication technology has been put forward higher requirements. Intelligent wireless terminals have also changed the human production effiency and life style. Internet of Things (IoTs), smart home, smart city, wearable system and other emerging markets force wireless communication integrated circuit (IC) to be more monolithic, lower power consumption and higher energy efficiency. As a significant block in wireless communication IC system, phase-locked loop (PLL) affects the bit error rate of corresponding communication system. A charge pump phase-locked loop (CPPLL) with the output frequency range from 1.5 GHz to 3.0 GHz is designed in this thesis based on SMIC 40 nm process.Charge pump (CP) determine the performance of in-band noise and spur. Non-ideal effects of CP generate ripple on the control voltage then periodic modulate the voltage controlled oscillator (VCO) and produce reference spur which decrease the performance of output noise. The static current mismatch is the main factor of non-ideal effects.A proposed dynamic current matching CP is designed in this thesis that improved the performance of reference spur, he maxium current mismatch rate is 0.83% with the voltage range from 0.3V to 0.7V, and the reference spur reduce from-37.65dBc to -56.37dBc with compared to a traditional CP.Loop filter is a low-pass filter (LPF). It filter out high frequency harmonic on the control voltage then control the VCO output frequency, suppress the out-band phase noise. The bandwidth of the filter determine the performance of the PLL such as locking time, stability and reference spur.In this thesis, PLL adopt dual CP structure effectively reduce the area of the LPF.As a core circuit of PLL, performance of VCO directly affects the performance of PLL. Ring VCO and LC VCO are two different types of VCO. This thesis analyzes the work principle and mathematical model of VCO, a VCO based on delay cell is designed with a output frequency range from 1.5GHz to 3.0GHz, the phase noise is-86.84dB@1MHz when the output frequency is 3.0GHz.A PLL is designed base on SMIC 40 nm process.The supply voltage is 1.1V, output frequency range from 1.5GHz to 3.0GHz, core circuit area is 0.1 mm2, locking time is 60μs, power consumption is 3.5mW @3.0GHz, pk-pk jitter is 11.65ps @3GHz.