Research On The Technology Of Network Switching In Emergency Medical Support Information System

The emergency medical support information system has been widely used, which greatly improving the emergency disaster relief, the battlefield casualties injury and treatment information collection, processing, transmission and utilization efficiency. But the information is still restricted by network transmission efficiency. Therefore, Research efficient network switching technology, Improve the information transfer timeliness, has been the key subject of next research of emergency medical support information system.For emergency medical support information system, not only need to find a suitable switch fabric structure, and in need of the corresponding chip design scheme. Now our country gives strong support in the integrated circuit industry, to alleviate the current situation of the chip market monopolized by foreign. This is especially important for military requirements or information security. Therefore, emergency medical support information system requires network switching chip with independent design property. In addition, the complexity of large-scale application-specific integrated circuit design has increased dramatically in recent years, verification becomes the bottleneck of chip design and manufacturers. After much effort, there has found the solution which can speed up the verification process. This is a verification technology with coverage-driven function, combined with reusable methodology, which can significantly reduce the expenditure.To solve the complexity and difficulty of network switching chip design or verification, this thesis research and design the buffer management unit. Meanwhile, this paper also study digital IC verification methodology and apply it to the chip development process. This constrained random test save the time and resources greatly, improve the simulation efficiency and ensure the correctness of design. First, paper consider two aspects of resource use and working rate, looking for a better cache allocation and release algorithm, using Verilog HDL to describe the hardware design of Buffer Management Unit. Secondly, paper build the hardware simulation platform based on the UVM for BMU using System Verilog. Finally, paper set up the FPGA test platform for packet switching chip using Altera’s Stratix IV development board.The results shows that the cache allocation and release algorithm can allocate and recover the cache space effectively. The verification platform based UVM increased the efficiency of simulation substantially.