Research And FPGA Design Of An Improved PS-LDPC Codes

Due to its near Shannon limit error correcting capability, LDPC codes have been paid much attention in latest years. And the codes have been brought into LTE and 4G standards. In this context, improving the error correcting capability and hardware implementing of LDPC codes have always been the focus of research. Targeting these, optimization scheme for constructing large-grith PS-LDPC codes, as well as a configurable FPGA implementation scheme for these PS-LDPC codes have been proposed in this dissertation.This dissertation firstly summarized the related foundational theory of LDPC and PS-LDPC codes specifically, and analyzed the cause for un-optimized local girth-dwindlement performance. To optimize the girth characteristics of PS-LDPC codes, this dissertation proposed a PEG based cycle searching approach, which can be used in construction of both QC-LDPC codes and PS-LDPC codes. Such LDPC codes have achieved desired girth-dwindlement performances.Then an FPGA implementation model was presented in the dissertation. Firstly, this design adopts a mechanism of paths swithing, throuth which LLR messages are transferred. This mechanism has implemented the reusability of processing units in decoder architecture, which cuts down the hardware resource consumption by large. Secondly, the improved PS-LDPC codes guarantees error correcting capability. And then pipeline design was brought in the model, in order to implement a Gbps throughput performance. This sort of model can also be applied in hardware implementation of QC-LDPC codes with large-size submatrices structure.Finally, by hardware design and timing logic simulation tools, the synthesis performances such as BER, throughput and hardware consumption are presented. Such decoders with different parity-check matrices structures display pretty different synthesis performances. Thus variety of performances can be achieved by configurating the structure parameters of PS-LDPC matrix. Such configurable PS-LDPC decoders can be applied in future heterogeneous networks context, since that it can be flexibly configurated to face complex application requirements.