Research And Design On High Performance And Special Arithmetic Unit Based On FPGA

With the applications of automatic unit controller chip more widely, and its function are more and more mightiness, the complexity of design is increasing, its performance requirements are also getting higher and higher. The key components of controller chip are interface and terminals, and their performances are determined the level of the entire controller system's performance directly, therefore, people in-depth study the interface and terminals for the design of controller chips and continue to make progress. However arithmetic unit as part of controller chips, its performance also can infect performance of the entire controller system.The performance of most current arithmetic unit used in controller chip is lagging far behind the performance of interface.The design of traditional arithmetics not only have speed defect, but also have problem in area and power.The simple design of arithmetic unit which has smaller area and power due to the serial thinking of the cycle of calculation,so it has slower speed. The special design of high-performance arithmetic has larger area, and high power consumption with low performance, whose structure is more complicated, more difficult to implement with hardware.Based on FPGA arithmetic unit which is parts of the controller chip is designd under the control of real-time requirements, due to increase in size, on the basis of the controller chips used in the existing FPGA arithmetic unit to increase speed.And by improving performance of arithmetic unit to improve the performance of the controller chip or even controller system.First, the adder improvements: Through divising the calculation data, with the advantages and disadvantages of the current optimum performance carry-select algorithm and carry-lookahead algorithm and using the group ahead, the group binary options to improve the design method of traditional CLA. And the group also used the assembly line technology, to further enhance the computing speed adder.Second, the improving work of multiplier: for the algorithms of part-product, using the improved Booth algorithm to reduce the number of part-product.And in order to reduce redundancy in the calculate process using 5-2 compression to improve the traditional 4-2 compressed tree structure.Third, the improved design of division: designed and implemented the 32-bit Radix-16 SRT division. The divider as a result of each cycle will be four to place, to reduce the frequency of the cycle-bit computing. In addition, VerilogHDL coding surprisingly several times when calculated in advance the divisor, which is not used is calculated to reduce redundancy in the process of calculation.Finally, the design of the floating-point parts, mainly on the floating-point adder have been studied and improved: to achieve dual-channel structure of the division leader a prediction circuit (LOP) and fixed-point adder parallel implementation of the displacement of Mantissa achieve, To achieve a rapid shift register, and using improved CLA which was designed in this paper as one sentinel adder which used in this circuit structure.In this paper, the innovation: With the FPGA hardware design as well as the advantages of the achieve simplicity with VerilogHDL hardware description language programming designed the high-performace Basic-FPGA arithmetic unit. Mainly improved circuit structure and implement algorithms of traditional FPGA-based arithmetic unit in the most of controller chips to improve the performace of FPGA-based addition, multiplication and division and floating-point adder. To a certain extent improved the performance of the controller chip.