High-performance Digital Arithmetic Unit Design Research

Many numerically intensive applications require rapid execution of arithmetic operations. The computational demand goes beyond fast addition and multiplication, support for high-performance division and the elementary functions is becoming increasingly necessary. This thesis study the high-performance digital arithmetic hardware design issues to support these arithmetic operations, and IEEE-754 floating point numbers has been studied for these arithmetic operations. The author provides a balanced, comprehensive treatment and tradeoff of design computer arithmetic unit, covering almost all topics in arithmetic unit design and . circuit implementation that complement the architectural, algorithmic and circuit speedup techniques. The circuit speedup techniques mainly focus on CMOS VLSI technology.After study a series adders algorithms and architectures, the author design two high-performance adder in transistor and logic gate level.After study a series array multipliers algorithms and architectures, . the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill.In division operation, the author study a series high-performance division algorithms adopted by nowadays the state of arts microprocessor. Discuss how to construct the SRT algorithm quotient select logic for any radix and using the On-The-Fly plus Overlap skills to improve SRT performance. The reciprocal ROM structure is also mentioned by this thesis. The author use the Mathematica 4.0 software simulating the hardware execution of four step Goldschimilt algorithm and find the error analysis result. For frequent appearance elementary function operation in current multimedia applications, the hardware speedup techniques of computing elementary function have been included and also analyze the elementary function evaluation technique using in Intel IA-32 and IA-64microprocessor.In design of high-performance FP adder, the author completes a two stage pipelining dual path IEEE-754 FP adder architecture. This adder not only have high-performance in speed but also excellent in lower power by using channel select signal PathX. With the algorithmic skill, we save a full bits length CPA on IEEE-754 result rounding. This FP adder also support the parallel rounding.In design of high-performance FP multiplier, the author completes a two stage pipelining IEEE-754 FP multiplier architecture. This FP multiplier support the parallel rounding, saving a full bits length CPA on IEEE-754 result rounding and the result is calculated by somewhat shorter CPA.