2.5 Gbps High-speed VML Interface Circuit Design And Research

With the development of computer communication technology, human’s pursuit of CPU for performance and speed is getting higher and higher, and I/O interface technology faces increasing pressure and challenges at the same time. The SERDES serial differential technology becomes the mainstream of high-speed interface technology, with its high speed and stable ability gradually. Based on the deep understanding of SERDES technology, this thesis studies the main high-speed analog circuit interface section, and uses the SMIC 0.13 um Mixde Signal 1P8 M craft and VML interface technology to design a transceiver interface circuit which its speed is up to 2.5 Gbps.This thesis first discusses the advantages and disadvantages of various high-speed serial communication interface technology, and study the VML interface circuit design, especially in its key and nails. Secondly we introduces two commonly used high-speed differential interface technology LVDS and CML briefly.At last we compare these two technologies with VML, and summarize their advantages and disadvantages.Then on the basis of understanding to VML interface technology, we design the VML drive circuit. We use a negative self-bias feedback amplifier to design the voltage regulator circuit, and avoid the use of complex band-gap reference technology to reduce the circuit complexity and area effectively. We add the pre-emphasis circuit to the basis drive circuit for ensuring the quality of the transmission signal, and designed strength adjustable pre-emphasis circuit for different transmission data rate. So we can reduced the inter symbol interference, and the bit error rat. At last we use the simulation tools to verify this circuit design meets the indicator.We use a sense of amplifier-based high-speed flip-flops as the receiver, and suitably modify the traditional SAFF to enhance the high-speed sampling capability of receiver. In order to ensure the integrity of the signal, the receiver has added the impedance matching circuit and LOS(Loss of Signal) circuit to reduce the inter-symbol interference and bit error rate. At last we use simulation software to finish simulation verified.In the last part of the thesis, we give the final design layout and its simulation result, which result is conforming with the design specifications of the project. The project is being chip tapeout, and the subsequent testing and validation will be done in a later section.