Performance Optimization Of Simulator For High-throughput Many-core Processor

With the increasing popularity of Big Data applications, the scale of data grows rapidly, which is posing substantial challenges to the performance of processors. Improvement of high-throughput many-core processors in aspects of processing speed, power consumption per unit area and scalability turns out to be the research hotspot in the field of computer architecture. As a result of the high complexity and cost of chip manufacturing, software simulator as a key tool in the research of computer architecture plays an important role in several stages of architecture research. Since simulation speed is a key indicator in evaluating software simulators, especially during simulation of large-scale many-core architecture, it is critical that simulation speed should be improved.This thesis analyses the existing simulation techniques in detail and categories them as techniques that speed up every single instruction or instruction block, techniques that reduce number of instructions being simulated and techniques that make use of parallelized computing resources as well as improve the concurrency of simulation algorithm. Based on that, this paper proposes following two schemes to retrofit and optimize the simulation of high-throughput many-core processors.(1) Based on the idea of improving the simulation speed of single instruction or instruction block, this paper proposes the lookup table method to speed up instruction decoding. Since memory resource in host machine is relatively adequate, we can save as a table results of calculations that arise repeatedly. In this way, other appearances of the same calculation can be replaced by a single action of looking up the table. The PopCount problem, inspection of instruction condition field and trace cache that occurred during instruction decoding are speeded up with the lookup table method. Not only does the introduction of lookup table method improve the instruction simulation speed, but it also makes the code implementation more concise and flexible.(2) In order to make use of parallelized computing resources and concurrency of simulation algorithm, Parallel Discrete Event Simulation(PDES) framework that optimized in several aspects are designed and then implemented; Firstly, in this framework, the random event mapping model is applied as a event scheduling algorithm, which improves the workload balance of working threads significantly; After that, the cycle-by-cycle time advance algorithm was applied in the framework to eliminate high overhead of synchronization, which benefits from the introduction of red-black tree data structure to manage future event list; Meanwhile, in accordance with the single writer single reader model, this paper implements the future event list in a lock-free way, which avoids the heavy lock overhead during event scheduling; Finally, vast amounts of discrete data access requests in big data workloads show up as frequent memory operations from components during simulation, the memory pool scheme is introduced to manage them. With the memory pool scheme, massive number of small size memory allocation and deallocation operations are replaced with a very few number of large scale memory operations, Thanks to the reduction in number of memory operations, the efficiency of memory management improves significantly.Typical Big Data applications including WordCount, TeraSort and KMP are used as benchmarks in evaluation of proposed accelerating schemes. Experiment results show that lookup table scheme speeds up as much as 26.14 times in solving the PopCount problem. The overall performance achieves a 3.94 times improvement because of the optimization in PDES framework.