Design Of A Dual-field Point Multiplication Accelerator In Elliptic Curve Cryptography

The Elliptic Curve Cryptosystem(ECC)in the public key system has received more and more attention because of its advantages such as higher security strength than RSA.In this thesis,firstly,the hardware implementation scheme of the dual-field point multiplication(PM)accelerator are proposed starting with the hierarchical structure of point multiplication in ECC.Secondly,a high-parallel Montgomery modular multiplication implementation scheme and circuit based on sum-product separation and a dual-field integer multiplication unit based on non-logic ratio 4-Booth algorithm are proposed in this paper.The critical path of Montgomery modular multiplication and the dual-field integer multiplication is reduced by the method.Thirdly,a fast dual-field Montgomery modular inverse implementation scheme and circuit based on non-overflow modular addition are proposed.The overhead of reduction operation is eliminated and the running time of the dual-field Montgomery modular inverse is also decreased by replacing the modulo-subtraction operation with a non-overflow modular addition.Finnally,a scheduling scheme based on the parallel compression of two dual-field modular multipliers is designed in point-double(PD)and point-addition(PA)which limits the point-multiplier performance directly.The scheduling scheme of two dual-field modular multiplier is the most efficient way to implement PD and PA operation from the research which is in this paper.The running time and storage overhead of PA and PD are less by using parallel compression with two dual-field modular multipliers meanwhile,and the performance of point multiplication is improved.The design of the dual-field point multiplication accelerator circuit is completed in this thesis.The functional verification of system and module-level are done with a verification platform.In addition,the circuit design is optimized and synthesized by Design Compiler.Experimental results show that the area of design is 168,018?m~2 and the clock frequency is 388MHz.The time of a 256-bit PM operation is0.48ms in the prime field and 0.31ms in the binary domain field.