Design Of Optical-fiber Interface Based On FPGA And Communication Based On CPCI Bus

With the continuous development of semiconductor technology, the performance of processor has got a rapid growth over the last few decades and it improves the performance of the embedded system greatly. But the bus technology of embedded system interconnection does not obtain the corresponding development, which means the bus performance is becoming a limit of growth of embedded system performance.The paper is based on a radar signal processing system and designs a high-speed optical fiber communication interface based on the Xilinx Virtex-5 FPGA. The communication protocol is Rapid IO, which is developed by the Rapid IO Trade Association to improve embedded system interconnection bus rate. The Virtex-5 FPGA is connected with TS201 S DSP and receive data from DSP. Then the transaction package is generated in FPGA in the sender and unpacked on the receiving end. The design realizes the full-duplex communication between two signal processing boards. The design language is Verilog HDL and the Integrated Development Environment(IDE) is Xilinx ISE 14.7. The Modelsim is used for simulation.The radar signal processing system also need to realize the communication between the signal processing board and the host interface card through CPCI bus. CPCI bus is a bus interface standard put forward by the PCI Industrial Computer Manufacturers Group(PCIMG, PCI Industrial Computer Manufacturers Group) and it is Compatible with PCI bus. The signal processing board connects with the PCI 9656 bridge chip and the PCI 9656 bridge chip connects with FPGA. In order to realize the communication between the signal processing board and the host interface card, the PCI9656 bridge local bus interface must be designed and the corresponding driver on the host side must be developed. The development tool of driver is Win Driver and the development language is C++.After completion of high-speed optical fiber communication interface design, the simulation and actual test should be carried on. The Modlesim is used to perform behavioral simulation and post-route simulation. After the software simulation, the communication interface is tested by a test-platform to eliminate potential errors and prove the validity of the design. And in the last the interface speed is tested. CPCI bus communication design also need to be debugged and tested. The Chipscope is used to observe the FPGA internal signals and actual test proves that the design of optical fiber communication interface and the CPCI bus communication are correct.