Research Of Turbo Encoding And Decoding Multi-core DSP Implementation

Since Turbo codes were presented in 1993, due to its superior performance near the Shannon limit, it has been a hot topic of research. With the maturity of Turbo codes research, its application in the field of communication has become increasingly widespread. In this paper, Turbo codes and multicore Digital Signal Processor(DSP)(TMS320C6678) implementation techniques are studied.In Chapter 1, this paper introduces the background of Turbo codes’ s research and application, describes the basic principles of Turbo codes.In Chapter 2, this paper provides a brief overview of the entire system of the project, introduces the hardware platform of system implementation and multicore DSP’s(C6678) hardware and software platform. Subsequently, system requirements are introduced.In Chapter 3, the analysis and design of Turbo codes are introduced, including the introduction of the algorithms that include Maximum A Posteriori(MAP) algorithm, Log-MAP algorithm and the Max-Log-MAP algorithm and the introduction of simple block decoding structure, overlapping block decoding structure and state boundaries iterative decoding structure of several block decoding structures based on MAP decoding algorithm. This paper simulates the effects of different parameters on the performance of Turbo codes, and determines the parameters of DSP implementation of Turbo Codes. Compared the performance of several block decoding structures, select both performance and complexity advantage of the state boundaries iterative decoding structure as the ultimate multi-core DSP implementation structure. This paper analyzes Turbo Codes’ s BER performance of the undivided blocks, 4-block and 8-block state boundaries iterative decoding structure in the entire system. The Bit Error Rate(BER) performances meet the needs of the system.In Chapter 4, according to the parameters’ s design of Turbo codes, this paper implements encoding and decoding module on the multicore DSP. Implementation is divided into sending and receiving ends. That decoding module is based on TI SYS/BIOS real-time operating system and master-slave mode multi-core development framework, to achieve sub-block parallel decoding architecture. In addition, this paper outlines the C6678 implementation and optimization techniques.In Chapter 5, implementation of DSP were tested, the test results are consistent with Matlab simulation results.And Encoding and decoding module’s delays meets the system requirements. The entire system to be tested, the test results are consistent with theoretical results.Finally, dissertation is summarized in Chapter 6, and possible research direction in the future is also discussed.