Research Of TSV Transmission Model And High Reliable Transmission For 3D Integrated Circuit

3D-IC based on Through Silicon Via(TSV) vertical interconnection has become really promising to IC development because of the shorter interconnecting length of TSV, together with higher transmission bandwidth. However, transmission reliability has become a serious issue when there are more TSVs on one limited planar area.The research focuses on this issue by establishing noise model and theoretically studying all the TSV related noise issues, so as to propose some feasible optimization methods for 3D IC designs. The study in this paper includes coupling model for TSV and interposer structure, with both 3D model and mathematical S parameter model. Related signal integrity metrics like peak-to-peak noise, transmission delay and bit error rate will be studied. Optimization from system level will also be covered.The model in our work can reflect TSV high-speed issue under various circumstances well. The S-parameter function in our study matches well with the result given by EM solver. The related work on peak-to-peak noise and TSV transmission delay shows high accuracy with SPICE model. The analys is of transimission line in inhomogenes is multipul-layer and optimization, which is closely related to crosstalk issues in Si-Interposer, shows high accuracy with the results given by EM solver. The proposed optimization method based on data transmission behavior can greatly improve TSV bandwidth with small overhead, which shows high value to the cost-effective and high-reliable 3D-IC design.