Implementation Of System Controller Module And System Verification Of Real-time Uhd Fruc System

The digital television industry has entered the UHD(Ultra High Definition) time with the rapid development of digital video process and integrated circuit technique. In recent years, the frame rate of UHD display device has reached 120 Hz above in order to improve the video display effect.But UHD digital video can only be transmitted on low frame rate because of limited bandwidth, then unmatching problem in transimission frame rate and display frame rate is generatd. Without effective frame rate up conversion algorithm, the frame rate unmatching issue will result in ghost phenomenon and motion blur problem when displaying video. In this paper, we focus on System Controller Module which is the key module of UHD FRUC(Frame Rate Up Conversion) system and complete UHD FRUC System’s hardware verification work based on FPGA.At beginning, this paper introduces the UHD Frame Rate Up Conversion(UHD FRUC) algorithm structure based on 3DRS block matching algorithm. The UHD FRUC algorithm mainly include motion estimation, vector post process and motion interpolation. Motion estimation calculates the motion vector by adopting motion compensation technique. Vector post process refines motion vector to deal with motion unmatching problem in the block and improve the accuracy of motion interpolation. Motion interpolation generates the final interpolation frames.Then, this paper gives the design structure and implementation solution of System Controller Module in the UHD FRUC project. The module contains data control function and parameter control function. Data control function adopts slab process method to reduce the system’s updating bandwidth requirement and avoid clock cycles’ waste. Design of the four stage pipeline is used in data control function to complete the huge system data process requirement. Parameter control function uses inter APB Bus(Advanced Peripheral Bus) and intra Parameter Bus to accomplish parameters’ configuration and control. Next, System Controller Module completes the functional verification and synthesis based on Cadence software platform. Code coverage indicator is used to verify completeness of test. The circuit synthesis result means that the System Controller Module’s can reach 300 M frequency clock and meet the design requirement. Under 65 nm CMOS library, the System Controller Module’s synthesis area is 0.138mm2At last, this paper constructs the verification solution on FPGA. Base on the FPGA platform, this paper designs and completes the UHD FRUC System’s hardware verification work.