Algorithm Research And Hardware Implementation Of Motion Verctor Postprocessing In Frame Rate Conversion

As the rapid development of digital display technology and IC technology, digital television has higher and higher picture refresh rate and picture resolution. However, due to the inherent shoot rate of video source, low bandwidth or other reasons, many video frame rate is low. When the video with low frame rate displays at a high refresh rate of the digital monitor, the video has ghosting, blurring and other problems. Video frame rate conversion technology is an effective way to solve these problems. Hardware real-time algorithms and related circuit design on frame rate conversion(FRC) is studied in this paper.The FRC motion vector(MV) postprocessing is based on three-dimensional recursive search(3DRS) because of its low computational complexity and high efficiency. Due to the UHD video contains a tremendous amount of data, the real-time hardware algorithm should be easy to be parallel implemented. In order, this paper use spatial correlation designing the MV processing, to reduce the inaccurate value in MV field; In order to improve the smoothness of MV field, we design the location-related smoothing algorithm for reducing the blocking artifacts of the interpolation frame and improving MV field smooth; In addition, the mainstream interpolation algorithm is analyzed and a robust median interpolation algorithm is used for improving the image area that has wrong MV; The method of MV zoom is designed by analyzing the geometric characteristics and spatial correlation.The difficult and key point in this research is the MV postprocessing hardware structure and real-time implementation. In the article the hardware implementation is mainly based on 3DRS hardware framework. At first, the overall hardware construct is introduced, and the key module in my research is MV processing module and interpolation module. In addition, the function of two module and peripheral circuit is introduced. In order to realize the high speed MV process cache, the data reuse and system pipelining is used for increasing resource utilization rate; For MV smooth calculation module, the multi-pipeline calculation is used for reducing the number of clock cycle; For interpolation module, calculation module of on-chip scheme were analyzed, the parallel computing is used for the fast calculation of large amount of interpolation data, and time division multiplex access technology is used for reducing the hardware resource. Finally hardware module is performed by Verilog and software test system is written in C++ language, the synthesization and verification is performed in Cadence software platform. The results show that this design meets the 300 MHz frequency requirement, and in 65 nm CMOS technology, MV processing module and interpolation module take 0.45mm2 and 1.12mm2 in area respectively.