Design And Hardware Implementation Of On-Chip Pixel Cache In Frame Rate Conversion System

In the field of digital television, because of the inherent defects of theLCDs, there are some effects such motion blur and shadow, which willseriously impact the audience’s visual experience. An effective method isthe frame rate conversion, through which can improve the quality of thevideo display by improving the fps of the video and smoothing the motionof moving objects. In this thesis，we give the hardware architecture of theframe rate conversion system. From the necessary conditions of theimplemetion of the system, we design and develop the hardware circuit ofthe pixel cache which is the core module of the whole frame rate conversionsystem.In the hardware system, all the data to be processed is from pixel cache.According to the access formal, we divide the process into3stage’s pipeline.In this paper, the actual hardware demands are firstly given and then designthe data bit-widths, addressing method and data parallelism, arrange thecache RAM array in order to meet the period constrain of5ns. Then thepixel cache is divided into sub modules according to the function, it is aboutpre-load control, cache request access and output control three parts. All thearchitecture of each sub modele and implemetion details is given in thispaper. Third, in order to improve the convenience of SAD calcution andinterpolation, the data processing module is also designed including dataalignment and filter which achieve the function of data cutting out, sub-pixel calculation and sparse interpolationFurther more, we also optimize the design of pixel cache, using thesparse area method, and add the hardware implemetion of sparse storage andsparse interpolation. Analysis of the design showed that by using sparse area,can save almost half of the whole RAM capacity.Last, we use Verilog HDL to develop the design of this thesis, and useEDA tools to verify the design. In the constraint of200MHz operatingfrequency (about365cycles), this system can finish all the task of a block tointerpolate into three frames. The synthesis report shows that the modulepixel cache has area of3.722mm~2in65nm CMOS.