Design Of Dual-channel UART Based On The Process Of 0.13 UM CMOS

Universal asynchronous receiver/transmitter, commonly referred to as UART, which make use of the serial data bus, as an asynchronous receiver and transmitter, was used for communication between the asynchronous system. The bus is bidirectional communication, which can realize full-duplex data transmission. The UART was widely used in the computers、industrial control and other communication systems because of the advantages of less transmission wire、the transmission distance、higher reliability and the lower cost.The new generation computer system with a high-end processors, which greatly enhance the speed of data processing, can handle a large number of tasks in a short time. The operating voltage of these processors is typically 3.3V、2.5V or 1.8V. Therefor, the UART connected with CPU must be improved to further reduce the overhead of CPU, and promote the performance of overall system. To design a high-performance, the indexes of baud rate、the depth of FIFO、voltage and power consumption must be considered.This paper designed a dual channel UART which baud rate can be up to 5 Mbps, based on the structure of low resolution of clock proportion, with the support of SMIC 0.13 μm CMOS process, which supply voltage of PAD and core was 3.3V、1.8V.The low resolution of clock proportion, which replace the interger frequency division with the rational frequency division, can broaden the scope of the baud rate largely, and improve the transimission accuracy and performance of UART. In the meantime, the structure of multi-channel can makes multiple channel send and receive data at the same time, which improve the speed of data transmission greatly.In order to reduce the overhead of CPU, this paper designed a FIFO which depth was 64 byte for each receiver and transimitter, and it can realize block transmission with the cooperation of DMA operation. Meanwhile, this paper presents a interrupt mode which contains four level interruptions, including sending interruption 、 receiver interruption、receiving line state interruption and MODEM interruption, the interrupt mode reduces the number of visits greatly, so that the CPU can handle more tasks. In order to facilitate debugging and implemented function of diagnostic on chip, this paper also designed the write back mode. In addition, this paper also designed 14 interal registers for each channel, UART can work on different mode though configure the registers by the address. In order to reduce the power consumption of the system, gated clock was used to reduce the turnover rate of the clock signal, and operation separation was used to keep a certain unit static to reduce the dynamic consumption. The layout was designed under the process of SMIC 1P6 M. It is verified that when the frequency of system clock was 80 MHZ, the baud rate was 5 Mbps, the static power consumption was 45.32 mW, the area of the layout was 0.238mm2. Compared with the existing chips which have the similar functions, the depth of FIFO have increased, the indicator of power and area have largely decreased.