Based On Rational Number Frequency Division Frequency Synthesizer CPLD Design Method

The technology of frequency synthesis has been called many electronic systems heart . Use a frequency synthesizer to be able to produce electron frequency spectrum. Frequency source needing to have boundary high-accuracy , height are stable in advanced electron system in many . So the technology of frequency synthesis is very important. Originally, the thesis sets off from the angle studying and applying mainly , thorough analysis being in progress to the problem expounds and proves .The thesis is to design the rational number frequency divider system which we can set the number by ourselves that based on the technology of frequency synthesis . The system including keyboard ,LCD screen ,control system and frequency divider system .The signal processing is the nucleus of system designing and analysis of the theory. We can input the setting value and control signal to get the results of frequency divider and circuit designing by a series of signal processing in order to start a scaling-down process . The pivotal process is the frequency divider arithmetic which has direct influence on the frequency divide performance.The thesis introduced the basic concept ,the theory of technology and the application of working of frequency synthesis and frequency dividing technology firstly. And then have discussed frequency division circuit design and algorithmic design of frequency division.But I also comply with the function having analysed frequency division implement on frequency besides , high frequency sum frequency division works most including that frequency division can work data width, that rational numbers change the error becoming a decimal having one accuracy problem right away , adopt 16 data width therefore data width is the broader , the higher its accuracy, is 2^-16 since the decimal fixed point adopting time imports. The frequency division algorithm adopting time because of has been that asynchronization comes true , the frequency division component has moved towards but existence when working self one being going to consider the accumulator carriage arithmetic time again at the same time with different but different time lapse of component. Should secretly scheme against when simple therefore, frequency division implement maximal working band is that time lapse decides from the component , should secretly scheme against when complicated but, time decides frequency division implement maximal working band right away from the arithmetic. We can be what can be allotted frequency from 16 places and 32-bit accumulator carriage most high frequency can find out, digit expanded , necessity may bring about corresponding time lapse since the same component secretly scheming against. Even if another, working under the same data width,secretly scheming against complicated and simple , what being brought about time lapse is also different. These our being able to in simulated wave form, clear seeing that.The design uses hardware description language .To use VHDL to implement frequency divide arithmetic and hardwired connection designing .We use top-down design technique. We can synthesize RTL circuit chart after finished VHDL design. We can see the core of the circuit is the ACC which is consist of addend register and adder. In order to achieve interaction between human and frequency divider conveniently ,we use the MCU to control all the system .Keyboard can set the work status of the system and LCD screen can display it.This system can achieve the 16 bit digital input at its option and the output signal approaches the ideal one when it work at the low frequency. The frequency divider can work at the more than 50MHz frequency and it satisfied the research requirement.