The Optimization Study About Improve The IC Testing Yield And Reduce The Testing Time

With the further development of the semiconductor industry, IC testing evolved as a separate industry, throughout the entire period of the IC design, chipset production, packaging and applications. With the diversity product functional and complex functional design, it is a challenge for the testing. Improve the testing yield while reduce the testing time are two important factors. As a contradiction, how to find the balance point to obtain the best economic benefit is very important. Currently, IC is toward to industrialization, the testing time absolutely affecting the testing cost. The complex and larger-scale IC, it definite takes long testing time. Testing process is a time consuming process, when do the large-scale IC testing, it is necessary to consider the testing time and maximize the testing yield.In this paper, it committed to reduce the test time and improve the testing yield by upgrade hardware reliability and optimize test program. The main contributes as bellow:1. Solved the relay’s reliability issue by reducing relay’s damage to make the test results more accurate, thus to improve testing yield. Hot switching a common problem for relay, defined enough buffer time and use the same relay test in a group can avoid relay’s damaged/shortened life. After the TIU board’s relay was repaired, the retest rate reduced from ~9% to ~3%, meet the normal production target.2. Optimization Chipset B’s VCCAXG test. Even both ISVM and VSIM model can be used for test, but ISVM model is easier to detect the short issue, it can effectively avoid the defect chipset flow to client. Meanwhile, the test time shorten from VSIM model’s 133 msto ISVM model’s 64 ms, reduced ~52%.3. Optimization Bin43’s test patterns by adjusting some unreasonable Timing setting values. Thus reduce the abnormal failure which was identified as defective loss, gained ~0.2% yield improve.4. Optimization the test procedure, shorten the testing time. Focus on Vcc Continuity and SBFT modules, combined all the x CDPS pins which with the same test parameters, priority choice the parallel test, remove some extra delays, eventually simplify the test program’s content, reduced 0.8s test time.